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S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP) 128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with CosmoRAM
Data Sheet
PRELIMINARY
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Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
Preliminary
Notice On Data Sheet Designations
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP) 128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with CosmoRAM
Data Sheet
PRELIMINARY
Distinctive Characteristics
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General Description
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Flash Memory Density 256Mb 128Mb 64Mb
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Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
Preliminary
Product Selector Guide
Device-Model# 6:6-$< 6:6-%< 6:6-$$< 6:6-%$< 6:6-&$< 6:6-&7< 0E 0E 0E Flash Density pSRAM Density 0E Flash Speed (MHz) pSRAM Speed (MHz/ns) Supplier &RVPR 5$0 &RVPR 5$0 0E &RVPR 5$0 &RVPR 5$0 &RVPR 5$0 &RVPR 5$0 [[ PP EDOO [[ PP EDOO Package Availability Status 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\
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2
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
S71WS-J Based MCPs
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii Preliminary ..........................................................................................................ii Combination .......................................................................................................ii Full Production (No Designation on Document) ...................................ii MCP Features ........................................................................................................ 1
Persistent Protection Bit Lock ....................................................................... 38 Standby Mode ...................................................................................................... 39 Automatic Sleep Mode ..................................................................................... 39 RESET#: Hardware Reset Input ................................................................ 39 Output Disable Mode ...................................................................................40
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Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2
MCP Block Diagram .............................................................................................6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Lookahead Connection Diagram . . . . . . . . . . . . 10 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 14
TLA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ........................................................................................... 14 FTA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ............................................................................15 TLC080--80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package ............................................................................... 16 TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package .........17
Secured Silicon Sector Protection Bit ...................................................... 43 Hardware Data Protection ......................................................................... 43 Write Protect (WP#) .......................................................................................44 Low VCC Write Inhibit .................................................................................44 Write Pulse "Glitch" Protection ...............................................................44 Logical Inhibit ...................................................................................................44 Power-Up Write Inhibit ...............................................................................44
Common Flash Memory Interface (CFI) . . . . . . . 45
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Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62
S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . .20 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 22 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input/Output Descriptions . . . . . . . . . . . . . . . . . . .24 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 25
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Reading Array Data ........................................................................................... 62 Set Configuration Register Command Sequence ..................................... 62
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Read Mode Setting ......................................................................................... 63 Programmable Wait State Configuration ............................................... 63
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Standard wait-state Handshaking Option ...............................................64
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Read Mode Configuration ...........................................................................64
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VersatileIOTM (VIO) Control .............................................................................25 Requirements for Asynchronous Read Operation (Non-Burst) ..........25 Requirements for Synchronous (Burst) Read Operation ...................... 26 8-, 16-, and 32-Word Linear Burst with Wrap Around ......................27
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Burst Active Clock Edge Configuration .................................................. 65 RDY Configuration ........................................................................................ 65
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Configuration Register ......................................................................................27 Handshaking ..........................................................................................................27 Simultaneous Read/Write Operations with Zero Latency ................... 28 Writing Commands/Command Sequences ................................................ 28 Accelerated Program Operation .................................................................. 28 Autoselect Mode ................................................................................................ 29
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Reset Command .................................................................................................66 Autoselect Command Sequence .................................................................... 67 Enter/Exit Secured Silicon Sector Command Sequence ......................... 67 Program Command Sequence ........................................................................68 Unlock Bypass Command Sequence ........................................................68
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Chip Erase Command Sequence ...................................................................69 Sector Erase Command Sequence ................................................................70 Erase Suspend/Erase Resume Commands ................................................... 71
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Sector/Sector Block Protection and Unprotection ................................. 30
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Sector Protection ...........................................................................................34 Persistent Sector Protection ...........................................................................34 Persistent Protection Bit (PPB) ..................................................................35 Persistent Protection Bit Lock (PPB Lock) .............................................35 Dynamic Protection Bit (DYB) ...................................................................35
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Persistent Sector Protection Mode Locking Bit ........................................37 Password Protection Mode .............................................................................37 Password and Password Mode Locking Bit ................................................37 64-bit Password ...................................................................................................38
Password Program Command ....................................................................... 72 Password Verify Command ............................................................................. 73 Password Protection Mode Locking Bit Program Command .............. 73 Persistent Sector Protection Mode Locking Bit Program Command ........................................................................................... 73 Secured Silicon Sector Protection Bit Program Command .................. 73 PPB Lock Bit Set Command ............................................................................ 74 DPB Write/Erase/Status Command ............................................................. 74 Password Unlock Command .......................................................................... 74 PPB Program Command .................................................................................. 75 All PPB Erase Command .................................................................................. 75 PPB Status Command ....................................................................................... 75 PPB Lock Bit Status Command ...................................................................... 75 Command Definitions ....................................................................................... 76
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
3
Preliminary
Write Operation Status . . . . . . . . . . . . . . . . . . . . .79
DQ7: Data# Polling ............................................................................................79
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DQ6: Toggle Bit I ................................................................................................ 81
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CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . 114 Functional Description . . . . . . . . . . . . . . . . . . . . . 115
Asynchronous Operation (Page Mode) .......................................................115
DQ2: Toggle Bit II .............................................................................................. 82
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Reading Toggle Bits DQ6/DQ2 ......................................................................83 DQ5: Exceeded Timing Limits ....................................................................... 84 DQ3: Sector Erase Timer ................................................................................ 84
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Functional Description . . . . . . . . . . . . . . . . . . . . . 116
Synchronous Operation (Burst Mode) ........................................................116
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 85
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State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Initial/Standby State ............................................................................................117
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Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
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Asynchronous Operation State .....................................................................117
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Synchronous Operation State ........................................................................118
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Key to Switching Waveforms . . . . . . . . . . . . . . . 88 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 89
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Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Power-up ...............................................................................................................118 Configuration Register ......................................................................................118 CR Set Sequence ................................................................................................118 Power Down ........................................................................................................121 Burst Read/Write Operation ..........................................................................121
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AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
VCC Power-up ..................................................................................................... 89
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CLK Characterization ....................................................................................... 90
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91
Synchronous/Burst Read @ VIO = 1.8 V ...................................................... 91
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CLK Input Function ..........................................................................................122 ADV# Input Function .......................................................................................123 WAIT# Output Function ................................................................................123
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Address Latch by ADV# .................................................................................125 Burst Length ........................................................................................................125 Single Write .........................................................................................................125 Write Control ....................................................................................................126
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Asynchronous Mode Read @ VIO = 1.8 V ..................................................95
Burst Read Suspend ..........................................................................................126
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Burst Write Suspend ........................................................................................127
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Erase/Program Operations @ VIO = 1.8 V ................................................. 98
Burst Read Termination ..................................................................................127
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Burst Write Termination ................................................................................128
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . 129 Recommended Operating Conditions (See Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 129 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 131
Read Operation ..................................................................................................131 Write Operation ............................................................................................... 133 Synchronous Operation - Clock Input (Burst Mode) ............................134 Synchronous Operation - Address Latch (Burst Mode) .......................134 Synchronous Read Operation (Burst Mode) ............................................ 135 Synchronous Write Operation (Burst Mode) ..........................................136 Power Down Parameters ............................................................................... 137 Other Timing Parameters ............................................................................... 137 AC Test Conditions ......................................................................................... 137 AC Measurement Output Load Circuit .....................................................138
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Temporary Sector Unprotect ....................................................................... 107
4
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
)LJXUH $V\QFKURQRXV 5HDG 7LPLQJ %DVLF 7LPLQJ )LJXUH $V\QFKURQRXV 5HDG 7LPLQJ %DVLF 7LPLQJ )LJXUH $V\QFKURQRXV 5HDG 7LPLQJ 2( $GGUHVV $FFHVV )LJXUH $V\QFKURQRXV 5HDG 7LPLQJ /% 8% %\WH $FFHVV )LJXUH $V\QFKURQRXV 5HDG 7LPLQJ 3DJH $GGUHVV $FFHVV DIWHU &( &RQWURO $FFHVV )LJXUH $V\QFKURQRXV 5HDG 7LPLQJ 5DQGRP DQG 3DJH $GGUHVV $FFHVV )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ %DVLF 7LPLQJ )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ %DVLF 7LPLQJ )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ :( &RQWURO )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH $V\QFKURQRXV :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH $V\QFKURQRXV 5HDG :ULWH 7LPLQJ &( &RQWURO )LJXUH $V\QFKURQRXV 5HDG :ULWH 7LPLQJ &( :( 2( &RQWURO )LJXUH $V\QFKURQRXV 5HDG :ULWH 7LPLQJ 2( :( &RQWURO )LJXUH $V\QFKURQRXV 5HDG :ULWH 7LPLQJ 2( :( /% 8% &RQWURO )LJXUH &ORFN ,QSXW 7LPLQJ )LJXUH $GGUHVV /DWFK 7LPLQJ 6\QFKURQRXV 0RGH )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ 2( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ &( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ $'9 &RQWURO )LJXUH 6\QFKURQRXV 5HDG :$,7 2XWSXW 7LPLQJ &RQWLQXRXV 5HDG )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ 2( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ &( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG 7LPLQJ $'9 &RQWURO )LJXUH 6\QFKURQRXV :ULWH 7LPLQJ :( /HYHO &RQWURO )LJXUH 6\QFKURQRXV :ULWH 7LPLQJ :( 6LQJOH &ORFN 3XOVH &RQWURO )LJXUH 6\QFKURQRXV :ULWH 7LPLQJ $'9 &RQWURO )LJXUH 6\QFKURQRXV :ULWH 7LPLQJ :( /HYHO &RQWURO 6LQJOH :ULWH )LJXUH 0 6\QFKURQRXV 5HDG WR :ULWH 7LPLQJ &( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG WR :ULWH 7LPLQJ $'9 &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG WR :ULWH 7LPLQJ &( &RQWURO )LJXUH 0 6\QFKURQRXV 5HDG WR :ULWH 7LPLQJ $'9 &RQWURO )LJXUH 6\QFKURQRXV :ULWH WR 5HDG 7LPLQJ &( &RQWURO
)LJXUH 6\QFKURQRXV :ULWH WR 5HDG 7LPLQJ $'9 &RQWURO )LJXUH 3RZHUXS 7LPLQJ )LJXUH 3RZHUXS 7LPLQJ )LJXUH 3RZHU 'RZQ (QWU\ DQG ([LW 7LPLQJ )LJXUH 6WDQGE\ (QWU\ 7LPLQJ DIWHU 5HDG RU :ULWH )LJXUH &RQILJXUDWLRQ 5HJLVWHU 6HW 7LPLQJ $V\QFKURQRXV 2SHUDWLRQ )LJXUH &RQILJXUDWLRQ 5HJLVWHU 6HW 7LPLQJ 6\QFKURQRXV 2SHUDWLRQ
COSMORAM Type 1 - 1.8 V, 16 Mb
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 General Description . . . . . . . . . . . . . . . . . . . . . . . 169 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 171 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 171 Recommended Operating Conditions . . . . . . . . 171 Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 172 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172
Read Operation .................................................................................................172 Write Operation .............................................................................................. 173 Power Down Parameters ...............................................................................174 Other Timing Parameters ...............................................................................174 AC Test Conditions .........................................................................................174 AC Measurement Output Load Circuit .....................................................174
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 175
)LJXUH 5HDG 7LPLQJ %DVLF 7LPLQJ )LJXUH 5HDG 7LPLQJ 2( DQG $GGUHVV $FFHVV )LJXUH 5HDG 7LPLQJ /% 8% %\WH $FFHVV )LJXUH :ULWH 7LPLQJ %DVLF 7LPLQJ )LJXUH :ULWH 7LPLQJ :( &RQWURO )LJXUH :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH :ULWH 7LPLQJ :( /% 8% %\WH :ULWH &RQWURO )LJXUH 5HDG :ULWH 7LPLQJ &( &RQWURO )LJXUH 5HDG :ULWH 7LPLQJ &( :( 2( &RQWURO )LJXUH 5HDG :ULWH 7LPLQJ 2( :( &RQWURO )LJXUH 5HDG :ULWH 7LPLQJ 2( :( /% 8% &RQWURO )LJXUH 3RZHU8S 7LPLQJ )LJXUH 3RZHU'RZQ (QWU\ DQG ([LW 7LPLQJ )LJXUH 6WDQGE\ (QWU\ 7LPLQJ DIWHU 5HDG RU :ULWH
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 183
Revision Summary
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
5
Preliminary
MCP Block Diagram
F-VCC Flash-only Address Shared Address CLK F-WP# F-ACC (Note 3) F1-CE# OE# WE# F-RST# AVD# (Note 3) F2-CE# R-VCC A22 VCC VCCQ 16 VID 16 DQ15 to DQ0 CLK WP# ACC Flash 1 CE# Flash 2 OE# (Note 4) WE# RESET# RDY AVD# VCC
A22
DQ15 to DQ0
RDY VSS
R-CE1#
R-UB# R-LB# (Note 1) R-CE2 (Note 2) R-CRE
CLK (Note 5) WAIT# CE# I/O15 to I/O0 WE# OE# pSRAM UB# VSSQ LB# AVD# (Note 5)
1RWHV

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6
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Connection Diagrams
(CosmoRAM Type-based)
EDOO )LQH3LWFK %DOO *ULG $UUD\ &RVPR5$0EDVHG 3LQRXW 7RS 9LHZ %DOOV )DFLQJ 'RZQ
A1 NC B2 AVD# C2 WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 CE1#f J2 CE1#s K2 RFU L2 RFU M1 NC B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 LB#s D4 UB#s E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU B5 F2-CE# C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCCf K5 DQ11 L5 VCCf B6 RFU C6 WE# D6 CE2s E6 A20 F6 A23 G6 RFU H6 DQ4 J6 VCCs K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D9 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D10 A15 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU
A10 NC
Legend
Shared
1st Flash only
2nd Flash only
1st RAM only
Reserved for Future Use
M10 NC
1RWHV

,Q 0&3V EDVHG RQ D VLQJOH 6:6[[[- 6:6[[[- EDOO % LV 5)8 ,Q 0&3V EDVHG RQ WZR 6:6[[[- 6:6- EDOO % LV &( I RU )&( $GGUHVVHV DUH VKDUHG EWZHHQ )ODVK DQG 5$0 GHSHQGLQJ RQ WKH GHQVLW\ RI WKH S65$0 MCP 6:6-$ 6:6-% 6:6-$ 6:6-% 6:6-& Flash-only Addresses $$ $ $$ $$ $ Shared Addresses $$ $$ $$ $$ $$
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
7
Preliminary
MCP 6:6-&
Flash-only Addresses $
Shared Addresses $$
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6SHFLDO KDQGOLQJ LV UHTXLUHG IRU )ODVK 0HPRU\ SURGXFWV LQ )%*$ SDFNDJHV )ODVK PHPRU\ GHYLFHV LQ )%*$ SDFNDJHV PD\ EH GDPDJHG LI H[SRVHG WR XOWUDVRQLF FOHDQLQJ PHWK RGV 7KH SDFNDJH DQGRU GDWD LQWHJULW\ PD\ EH FRPSURPLVHG LI WKH SDFNDJH ERG\ LV H[SRVHG WR WHPSHUDWXUHV DERYH & IRU SURORQJHG SHULRGV RI WLPH
(CosmoRAM Type-based)
EDOO )LQH3LWFK %DOO *ULG $UUD\ &RVPR5$0EDVHG 3LQRXW 7RS 9LHZ %DOOV
Legend
A1 AVD# B1 WP# C1 A3 D1 A2 E1 A1 F1 A0 G1 CE1#f H1 CE1#s J1 RFU K1 RFU
A2 RFU B2 A7 C2 A6 D2 A5 E2 A4 F2 VSS G2 OE# H2 DQ0 J2 DQ8 K2 RFU
A3 CLK B3 LB#s C3 UB#s D3 A18 E3 A17 F3 DQ1 G3 DQ9 H3 DQ10 J3 DQ2 K3 RFU
A4 F2-CE# B4 ACC C4 RESET# D4 RDY E4 RFU F4 RFU G4 DQ3 H4 VCCf J4 DQ11 K4 VCCf
A5 RFU B5 WE# C5 CE2s D5 A20 E5 A23 F5 RFU G5 DQ4 H5 VCCs J5 RFU K5 RFU
A6 RFU B6 A8 C6 A19 D6 A9 E6 A10 F6 DQ6 G6 DQ13 H6 DQ12 J6 DQ5 K6 RFU
A7 RFU B7 A11 C7 A12 D7 A13 E7 A14 F7 RFU G7 DQ15 H7 DQ7 J7 DQ14 K7 RFU
A8 RFU B8 RFU C8 A15 D8 A21 E8 A22 F8 A16 G8 RFU H8 VSS J8 RFU K8 RFU
Shared
1st Flash only
2nd Flash only
1st RAM only
Reserved for Future Use
1RWHV

,Q 0&3V EDVHG RQ D VLQJOH 6:6[[[- 6:6[[[- EDOO % LV 5)8 ,Q 0&3V EDVHG RQ WZR 6:6[[[- 6:6- EDOO % LV &( I RU )&( $GGUHVVHV DUH VKDUHG EWZHHQ )ODVK DQG 5$0 GHSHQGLQJ RQ WKH GHQVLW\ RI WKH S65$0 7KH EDOO SLQRXW LV DSSOLFDEOH RQO\ WR WKRVH 0&3V ZLWK )ODVK GHQVLW\ RI 0E RU 0E )RU DOO WKH RWKHU 0&3V LQFOXGHG LQ WKLV GDWDVKHHW SOHDVH XVH WKH EDOO SLQRXW IRU GHVLJQ MCP 6:6-$ 6:6-% Flash-only Addresses $$ $ Shared Addresses $$ $$
8
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
MCP 6:6-$ 6:6-% 6:6-& 6:6-&
Flash-only Addresses $$ $$ $ $
Shared Addresses $$ $$ $$ $$
6SHFLDO +DQGOLQJ ,QVWUXFWLRQV )RU )%*$ 3DFNDJH
6SHFLDO KDQGOLQJ LV UHTXLUHG IRU )ODVK 0HPRU\ SURGXFWV LQ )%*$ SDFNDJHV )ODVK PHPRU\ GHYLFHV LQ )%*$ SDFNDJHV PD\ EH GDPDJHG LI H[SRVHG WR XOWUDVRQLF FOHDQLQJ PHWK RGV 7KH SDFNDJH DQGRU GDWD LQWHJULW\ PD\ EH FRPSURPLVHG LI WKH SDFNDJH ERG\ LV H[SRVHG WR WHPSHUDWXUHV DERYH & IRU SURORQJHG SHULRGV RI WLPH
9
S71WS-J_04A2 August 19, 2005
Preliminary
Lookahead Connection Diagram
Legend: A1 DNU B1 DNU A2 DNU B2 DNU C2 AVD# D2 F-WP# E2 A3 F2 A2 G2 A1 H2 A0 J2 F1-CE# K2 R1-CE1# L2 L2 R-VCC M2 A27 N1 F-DQS0 P1 DNU N2 DNU P2 DNU C3 VSS D3 A7 E3 A6 F3 A5 G3 A4 H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 A26 C4 CLK D4 C5 F2-CE# D5 C6 F-VCC D6 WE# E6 R1-CE2 F6 A20 G6 A23 H6 R2-CE2 J6 DQ4 K6 R1-VCC L6 A25 M6 F4-CE# C7 F-CLK D7 A8 E7 A19 F7 A9 G7 A10 H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 R-VCCQ C8 R-OE# D8 A11 E8 A12 F8 A13 G8 A14 H8 A24 J8 DQ15 K8 DQ7 L8 DQ14 M8 F-VCCQ A9 DNU B9 DNU C9 F2-OE# D9 F3-CE# E9 A15 F9 A21 G9 A22 H9 A16 2nd RAM Only J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS J5 DQ3 K5 K5 F-VCC L5 DQ11 M5 F-VCC J2 DNU K9 VSS L9 WP#/ACC M9 R-CLK N9 DNU P9 DNU N10 F-DQS-1 P10 DNU xRAM Shared Only 1st RAM Only Flash Only Flash/Data Shared Only A10 DNU B10 DNU MirrorBit Data-storage Only Shared or DNU (Do Not Use)
R-LB# WP#/ACC E4 R-UB# F4 A18 G4 A17 H4 DQ1 E5 F-RST# F5 RDY G5 R2-CE1 H5 R2-VCC
1st Flash Only
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August 19, 2005 S71WS-J_04A2
10
Preliminary
Input/Output Descriptions
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
11
Preliminary
Ordering Information
7KH RUGHU QXPEHU LV IRUPHG E\ D YDOLG FRPELQDWLRQV RI WKH IROORZLQJ
S71WS 256 J C0 BA W A K 0
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S71WS064JA0 Valid Combinations (WS064J Flash + 16Mb pSRAM) Base Ordering Part Number 6:6-$%$:< 6:6-$%):< Package Marking :6-$%$:< :6-$%):< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
1RWHV 7\SH LV VWDQGDUG 6SHFLI\ RWKHU RSWLRQV DV UHTXLUHG %*$ SDFNDJH PDUNLQJ RPLWV OHDGLQJ 6 DQG SDFNLQJ W\SH GHVLJQDWRU IURP RUGHULQJ SDUW QXPEHU
12
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
S71WS064JB0 Valid Combinations (WS064J Flash + 32Mb pSRAM) Base Ordering Part Number 6:6-%%$:< 6:6-%%):< Package Marking :6-%%$:< :6-%%):< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
1RWHV 7\SH LV VWDQGDUG 6SHFLI\ RWKHU RSWLRQV DV UHTXLUHG %*$ SDFNDJH PDUNLQJ RPLWV OHDGLQJ 6 DQG SDFNLQJ W\SH GHVLJQDWRU IURP RUGHULQJ SDUW QXPEHU
S71WS128JA0 Valid Combinations (WS128J Flash + 16Mb pSRAM) Base Ordering Part Number 6:6-$%$:$< 6:6-$%):$< Package Marking :6-$%$:$< :6-$%):$< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
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S71WS128JB0 Valid Combinations (WS128J Flash + 32Mb pSRAM) Base Ordering Part Number 6:6-%%$:$< 6:6-%%):$< Package Marking :6-%%$:$< :6-%%):$< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
1RWHV 7\SH LV VWDQGDUG 6SHFLI\ RWKHU RSWLRQV DV UHTXLUHG %*$ SDFNDJH PDUNLQJ RPLWV OHDGLQJ 6 DQG SDFNLQJ W\SH GHVLJQDWRU IURP RUGHULQJ SDUW QXPEHU
S71WS128JC0 Valid Combinations (WS128J Flash + 64Mb pSRAM) Base Ordering Part Number 6:6-&%$:$< 6:6-&%):$< Package Marking :6-&%$:$< :6-&%):$< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
1RWHV 7\SH LV VWDQGDUG 6SHFLI\ RWKHU RSWLRQV DV UHTXLUHG %*$ SDFNDJH PDUNLQJ RPLWV OHDGLQJ 6 DQG SDFNLQJ W\SH GHVLJQDWRU IURP RUGHULQJ SDUW QXPEHU
S71WS256JC0 Valid Combinations (2 x WS128J Flash + 64Mb pSRAM) Base Ordering Part Number 6:6-&%$:7< 6:6-&%):7< Package Marking :6-&%$:7< :6-&%):7< Temperature Range & WR & & WR & Burst Speed 0+] Material Set 3EIUHH FRPSOLDQW 3EIUHH 9DOLG &RPELQDWLRQV Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Supplier &RVPR5$0
1RWHV 7\SH LV VWDQGDUG 6SHFLI\ RWKHU RSWLRQV DV UHTXLUHG %*$ SDFNDJH PDUNLQJ RPLWV OHDGLQJ 6 DQG SDFNLQJ W\SH GHVLJQDWRU IURP RUGHULQJ SDUW QXPEHU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
13
Preliminary
Physical Dimensions
TLA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
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3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
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EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 TLA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10, E1,E10,F1,F10,G1,G10, H1,H10,J1,J10,K1,K10,L1,L10, M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
14
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
FTA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
INDEX MARK PIN A1 CORNER 10
3 2 1 MLKJ HG F EDC BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
84X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 FTA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 1.02 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.40 --1.17 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3388 \ 16-038.21a
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
15
Preliminary
TLC080--80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D
0.15 C (2X)
8 7 6
A
D1 eD
SE 7 E1
E eE
5 4 3 2 1
PIN A1 CORNER
INDEX MARK 10
K
J
H
G
F
E
D
C
B
A
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW
M CAB MC
80X
0.15 0.08
b
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLC 080 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.17 0.81 NOM ------9.00 BSC. 7.00 BSC. 7.20 BSC. 5.60 BSC. 10 8 80 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3430 \ 16-038.22 \ 10.15.04
16
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D
0.15 C (2X)
8 7 6
A
D1 eD
SE 7 E1
E eE
5 4 3 2 1
INDEX MARK PIN A1 CORNER 9
K
J
H
G
F
E
D
C
B
A
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
80X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 TSC 080 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.17 0.81 NOM ------9.00 BSC. 7.00 BSC. 7.20 BSC. 5.60 BSC. 10 8 80 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3496 \ 16-038.22 \ 5.20.05
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
17
S29WS128/064J
Flash Family for Multi-Chip Products (MCP) 128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PRELIMINARY
Distinctive Characteristics
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Issue Date August 19, 2005
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Publication Number S71WS-J_04 Revision A
Amendment 2
Preliminary
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
19
Preliminary
General Description
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20
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
21
Preliminary
Product Selector Guide
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22
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Block Diagram of Simultaneous Operation Circuit
VCC VSS VIO Y-Decoder
Bank A Address
Latches and Control Logic
VSSIO
DQ15-DQ0
Bank A
Amax-A0 X-Decoder OE#
Bank B Address
Latches and Control Logic
Y-Decoder
DQ15-DQ0
Bank B
WP# ACC RESET# WE# CE# AVD# RDY DQ15-DQ0
Amax-A0
X-Decoder DQ15-DQ0 Status
STATE CONTROL & COMMAND REGISTER
Amax-A0
Control
X-Decoder
Latches and Control Logic
Y-Decoder
Bank C Address
Bank C
DQ15-DQ0
Amax-A0
Amax-A0 X-Decoder
Bank D Address
Latches and Control Logic
Y-Decoder
Bank D
DQ15-DQ0
$PD[ :6- $ :6- $
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
23
Preliminary
Input/Output Descriptions
$PD[$ '4'4 &( 2( :( 9&& 9,2 966 1& 5'< $GGUHVV LQSXWV 'DWD LQSXWRXWSXW &KLS (QDEOH LQSXW $V\QFKURQRXV UHODWLYH WR &/. IRU WKH %XUVW PRGH 2XWSXW (QDEOH LQSXW $V\QFKURQRXV UHODWLYH WR &/. IRU WKH %XUVW PRGH :ULWH (QDEOH LQSXW 'HYLFH 3RZHU 6XSSO\ 9 ,QSXW 2XWSXW %XIIHU 3RZHU 6XSSO\ 9 *URXQG 1R &RQQHFW QRW FRQQHFWHG LQWHUQDOO\ 5HDG\ RXWSXW ,Q 6\QFKURQRXV 0RGH LQGLFDWHV WKH VWDWXV RI WKH %XUVW UHDG /RZ GDWD QRW YDOLG DW H[SHFWHG WLPH +LJK GDWD YDOLG ,Q $V\QFKURQRXV 0RGH LQGLFDWHV WKH VWDWXV RI WKH LQWHUQDO SURJUDP DQG HUDVH IXQFWLRQ /RZ SURJUDPHUDVH LQ SURJUHVV +LJK ,PSHGDQFH SURJUDPHUDVH FRPSOHWHG &/. LV QRW UHTXLUHG LQ DV\QFKURQRXV PRGH ,Q EXUVW PRGH DIWHU WKH LQLWLDO ZRUG LV RXWSXW VXEVHTXHQW DFWLYH HGJHV RI &/. LQFUHPHQW WKH LQWHUQDO DGGUHVV FRXQWHU $GGUHVV 9DOLG LQSXW ,QGLFDWHV WR GHYLFH WKDW WKH YDOLG DGGUHVV LV SUHVHQW RQ WKH DGGUHVV LQSXWV $PD[$ /RZ IRU DV\QFKURQRXV PRGH LQGLFDWHV YDOLG DGGUHVV IRU EXUVW PRGH FDXVHV VWDUWLQJ DGGUHVV WR EH ODWFKHG +LJK GHYLFH LJQRUHV DGGUHVV LQSXWV +DUGZDUH UHVHW LQSXW /RZ GHYLFH UHVHWV DQG UHWXUQV WR UHDGLQJ DUUD\ GDWD +DUGZDUH ZULWH SURWHFW LQSXW $W 9,/ GLVDEOHV SURJUDP DQG HUDVH IXQFWLRQV LQ WKH IRXU RXWHUPRVW VHFWRUV 6KRXOG EH DW 9,+ IRU DOO RWKHU FRQGLWLRQV $W 9++ DFFHOHUDWHV SURJUDPPLQJ DXWRPDWLFDOO\ SODFHV GHYLFH LQ XQORFN E\SDVV PRGH $W 9,/ ORFNV DOO VHFWRUV 6KRXOG EH DW 9,+ IRU DOO RWKHU FRQGLWLRQV
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5(6(7 :3 $&&
1RWH $PD[
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24
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Device Bus Operations
7KLV VHFWLRQ GHVFULEHV WKH UHTXLUHPHQWV DQG XVH RI WKH GHYLFH EXV RSHUDWLRQV ZKLFK DUH LQLWLDWHG WKURXJK WKH LQWHUQDO FRPPDQG UHJLVWHU 7KH FRPPDQG UHJLVWHU LWVHOI GRHV QRW RFFXS\ DQ\ DGGUHVVDEOH PHPRU\ ORFDWLRQ 7KH UHJLVWHU LV FRP SRVHG RI ODWFKHV WKDW VWRUH WKH FRPPDQGV DORQJ ZLWK WKH DGGUHVV DQG GDWD LQIRUPDWLRQ QHHGHG WR H[HFXWH WKH FRPPDQG 7KH FRQWHQWV RI WKH UHJLVWHU VHUYH DV LQSXWV WR WKH LQWHUQDO VWDWH PDFKLQH 7KH VWDWH PDFKLQH RXWSXWV GLFWDWH WKH IXQFWLRQ RI WKH GHYLFH 7DEOH OLVWV WKH GHYLFH EXV RSHUDWLRQV WKH LQSXWV DQG FRQ WURO OHYHOV WKH\ UHTXLUH DQG WKH UHVXOWLQJ RXWSXW 7KH IROORZLQJ VXEVHFWLRQV GHVFULEH HDFK RI WKHVH RSHUDWLRQV LQ IXUWKHU GHWDLO
Table 1.
Device Bus Operations
&/. 6HH 1RWH ; ; ; / /
2SHUDWLRQ $V\QFKURQRXV 5HDG $GGUHVVHV /DWFKHG $V\QFKURQRXV 5HDG $GGUHVVHV 6WHDG\ 6WDWH $V\QFKURQRXV :ULWH 6\QFKURQRXV :ULWH 6WDQGE\ &( +DUGZDUH 5HVHW %XUVW 5HDG 2SHUDWLRQV /RDG 6WDUWLQJ %XUVW $GGUHVV $GYDQFH %XUVW WR QH[W DGGUHVV ZLWK DSSURSULDWH 'DWD SUHVHQWHG RQ WKH 'DWD %XV 7HUPLQDWH FXUUHQW %XUVW UHDG F\FOH 7HUPLQDWH FXUUHQW %XUVW UHDG F\FOH YLD 5(6(7 7HUPLQDWH FXUUHQW %XUVW UHDG F\FOH DQG VWDUW QHZ %XUVW UHDG F\FOH
/HJHQG / /RJLF + /RJLF ; 1RWH 'HIDXOW DFWLYH HGJH RI &/. LV WKH ULVLQJ HGJH
&( / / / / + ;
2( / / + + ; ;
:( + + / / ; ;
$ $GGU ,Q $GGU ,Q $GGU ,Q $GGU ,Q +,*+ = +,*+ =
'4 ,2 ,2 ,2 ,2 +,*+ = +,*+ =
5(6(7 + + + + + /
$9'
; ;
; ;
/ / + ; /
; / ; ; ;
+ + + + +
$GGU ,Q +,*+ = +,*+ = +,*+ = +,*+ =
; %XUVW 'DWD 2XW +,*+ = +,*+ = ,2
+ + + / + ; + ; ;
'RQW &DUH
VersatileIOTM (VIO) Control
7KH 9HUVDWLOH,2 9,2 FRQWURO DOORZV WKH KRVW V\VWHP WR VHW WKH YROWDJH OHYHOV WKDW WKH GHYLFH JHQHUDWHV DW LWV GDWD RXWSXWV DQG WKH YROWDJHV WROHUDWHG DW LWV GDWD LQ SXWV WR WKH VDPH YROWDJH OHYHO WKDW LV DVVHUWHG RQ WKH 9,2 SLQ
Requirements for Asynchronous Read Operation (Non-Burst)
7R UHDG GDWD IURP WKH PHPRU\ DUUD\ WKH V\VWHP PXVW ILUVW DVVHUW D YDOLG DGGUHVV RQ $PD[$$$ IRU :6- DQG $$ IRU :6- ZKLOH GULYLQJ $9' DQG &( WR 9,/ :( VKRXOG UHPDLQ DW 9,+ 7KH ULVLQJ HGJH RI $9' ODWFKHV WKH DGGUHVV 7KH GDWD ZLOO DSSHDU RQ '4'4 6LQFH WKH PHPRU\ DUUD\ LV GLYLGHG LQWR IRXU EDQNV HDFK EDQN UHPDLQV HQDEOHG IRU UHDG DFFHVV XQWLO WKH FRPPDQG UHJLVWHU FRQWHQWV DUH DOWHUHG $GGUHVV DFFHVV WLPH W$&& LV HTXDO WR WKH GHOD\ IURP VWDEOH DGGUHVVHV WR YDOLG RXWSXW GDWD 7KH FKLS HQDEOH DFFHVV WLPH W&( LV WKH GHOD\ IURP WKH VWDEOH DG
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
25
Preliminary
GUHVVHV DQG VWDEOH &( WR YDOLG GDWD DW WKH RXWSXWV 7KH RXWSXW HQDEOH DFFHVV WLPH W2( LV WKH GHOD\ IURP WKH IDOOLQJ HGJH RI 2( WR YDOLG GDWD DW WKH RXWSXW 7KH LQWHUQDO VWDWH PDFKLQH LV VHW IRU UHDGLQJ DUUD\ GDWD LQ DV\QFKURQRXV PRGH XSRQ GHYLFH SRZHUXS RU DIWHU D KDUGZDUH UHVHW 7KLV HQVXUHV WKDW QR VSXULRXV DOWHUDWLRQ RI WKH PHPRU\ FRQWHQW RFFXUV GXULQJ WKH SRZHU WUDQVLWLRQ
Requirements for Synchronous (Burst) Read Operation
7KH GHYLFH LV FDSDEOH RI FRQWLQXRXV VHTXHQWLDO EXUVW RSHUDWLRQ DQG OLQHDU EXUVW RSHUDWLRQ RI D SUHVHW OHQJWK :KHQ WKH GHYLFH ILUVW SRZHUV XS LW LV HQDEOHG IRU DV\QFKURQRXV UHDG RSHUDWLRQ 3ULRU WR HQWHULQJ EXUVW PRGH WKH V\VWHP VKRXOG GHWHUPLQH KRZ PDQ\ ZDLW VWDWHV DUH GHVLUHG IRU WKH LQLWLDO ZRUG W,$&& RI HDFK EXUVW DFFHVV ZKDW PRGH RI EXUVW RSHUDWLRQ LV GHVLUHG ZKLFK HGJH RI WKH FORFN ZLOO EH WKH DFWLYH FORFN HGJH DQG KRZ WKH 5'< VLJQDO ZLOO WUDQVLWLRQ ZLWK YDOLG GDWD 7KH V\VWHP ZRXOG WKHQ ZULWH WKH FRQILJXUDWLRQ UHJLVWHU FRPPDQG VHTXHQFH 6HH 6HW &RQILJXUDWLRQ 5HJLVWHU &RPPDQG 6HTXHQFH VHFWLRQ RQ SDJH DQG &RPPDQG 'HILQLWLRQV VHFWLRQ RQ SDJH IRU IXUWKHU GHWDLOV 2QFH WKH V\VWHP KDV ZULWWHQ WKH 6HW &RQILJXUDWLRQ 5HJLVWHU FRPPDQG VH TXHQFH WKH GHYLFH LV HQDEOHG IRU V\QFKURQRXV UHDGV RQO\ 7KH LQLWLDO ZRUG LV RXWSXW W,$&& DIWHU WKH DFWLYH HGJH RI WKH ILUVW &/. F\FOH 6XE VHTXHQW ZRUGV DUH RXWSXW W%$&& DIWHU WKH DFWLYH HGJH RI HDFK VXFFHVVLYH FORFN F\FOH ZKLFK DXWRPDWLFDOO\ LQFUHPHQWV WKH LQWHUQDO DGGUHVV FRXQWHU 1RWH WKDW WKH GHYLFH KDV D IL[HG LQWHUQDO DGGUHVV ERXQGDU\ WKDW RFFXUV HYHU\ ZRUGV VWDUWLQJ DW DGGUHVV )K 'XULQJ WKH WLPH WKH GHYLFH LV RXWSXWWLQJ GDWD DW WKLV IL[HG LQWHUQDO DGGUHVV ERXQG DU\ DGGUHVV )K )K %)K HWF D WZR F\FOH ODWHQF\ RFFXUV EHIRUH GDWD DSSHDUV IRU WKH QH[W DGGUHVV DGGUHVV K K &K HWF $GGLWLRQDOO\ ZKHQ WKH GHYLFH LV UHDG IURP DQ RGG DGGUHVV ZDLW VWDWH LV LQVHUWHG ZKHQ WKH DGGUHVV SRLQWHU FURVVHV WKH ILUVW ERXQGDU\ WKDW RFFXUV HYHU\ ZRUGV )RU LQVWDQFH LI WKH GHYLFH LV UHDG IURP $K RGG ZDLW VWDWH LV LQVHUWHG EHIRUH WKH GDWD RI K LV RXWSXW 7KLV ZDLW VWDWHV LV LQVHUWHG DW RQO\ WKH ILUVW ZRUGV ERXQGDU\ 7KHQ LI WKH GHYLFH LV UHDG IURP WKH RGG DGGUHVV ZLWKLQ WKH ODVW ZRUGV RI ZRUG ERXQGDU\ DGGUHVV K K (K D WKUHH F\FOH ODWHQF\ RFFXUV EHIRUH GDWD DSSHDUV IRU WKH QH[W DGGUHVV DGGUHVV K 7KH 5'< RXWSXW LQGLFDWHV WKLV FRQGLWLRQ WR WKH V\VWHP E\ SXOVLQJ GHDFWLYH ORZ 6HH )LJXUH /DWHQF\ ZLWK %RXQGDU\ &URVVLQJ RQ SDJH 7KH GHYLFH ZLOO FRQWLQXH WR RXWSXW VHTXHQWLDO EXUVW GDWD ZUDSSLQJ DURXQG WR DG GUHVV K DIWHU LW UHDFKHV WKH KLJKHVW DGGUHVVDEOH PHPRU\ ORFDWLRQ XQWLO WKH V\VWHP GULYHV &( KLJK 5(6(7 ORZ RU $9' ORZ LQ FRQMXQFWLRQ ZLWK D QHZ DGGUHVV 6HH 7DEOH 'HYLFH %XV 2SHUDWLRQV RQ SDJH ,I WKH KRVW V\VWHP FURVVHV WKH EDQN ERXQGDU\ ZKLOH UHDGLQJ LQ EXUVW PRGH DQG WKH GHYLFH LV QRW SURJUDPPLQJ RU HUDVLQJ D WZRF\FOH ODWHQF\ ZLOO RFFXU DV GH VFULEHG DERYH LQ WKH VXEVHTXHQW EDQN ,I WKH KRVW V\VWHP FURVVHV WKH EDQN ERXQGDU\ ZKLOH WKH GHYLFH LV SURJUDPPLQJ RU HUDVLQJ WKH GHYLFH ZLOO SURYLGH UHDG VWDWXV LQIRUPDWLRQ 7KH FORFN ZLOO EH LJQRUHG $IWHU WKH KRVW KDV FRPSOHWHG VWDWXV UHDGV RU WKH GHYLFH KDV FRPSOHWHG WKH SURJUDP RU HUDVH RSHUDWLRQ WKH KRVW FDQ UHVWDUW D EXUVW RSHUDWLRQ XVLQJ D QHZ DGGUHVV DQG $9' SXOVH
26
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary DQG :RUG /LQHDU %XUVW ZLWK :UDS $URXQG
7KH UHPDLQLQJ WKUHH EXUVW UHDG PRGHV DUH RI WKH OLQHDU ZUDS DURXQG GHVLJQ LQ ZKLFK D IL[HG QXPEHU RI ZRUGV DUH UHDG IURP FRQVHFXWLYH DGGUHVVHV ,Q HDFK RI WKHVH PRGHV WKH EXUVW DGGUHVVHV UHDG DUH GHWHUPLQHG E\ WKH JURXS ZLWKLQ ZKLFK WKH VWDUWLQJ DGGUHVV IDOOV 7KH JURXSV DUH VL]HG DFFRUGLQJ WR WKH QXPEHU RI ZRUGV UHDG LQ D VLQJOH EXUVW VHTXHQFH IRU D JLYHQ PRGH VHH 7DEOH
Table 2. Burst Address Groups
0RGH ZRUG ZRUG ZRUG *URXS 6L]H ZRUGV ZRUGV ZRUGV *URXS $GGUHVV 5DQJHV K )K K )K )K )K )K )K )K
$V DQ H[DPSOH LI WKH VWDUWLQJ DGGUHVV LQ WKH ZRUG PRGH LV K WKH DGGUHVV UDQJH WR EH UHDG ZRXOG EH )K DQG WKH EXUVW VHTXHQFH ZRXOG EH $% &'()KHWF 7KH EXUVW VHTXHQFH EHJLQV ZLWK WKH VWDUWLQJ DGGUHVV ZULW WHQ WR WKH GHYLFH EXW ZUDSV EDFN WR WKH ILUVW DGGUHVV LQ WKH VHOHFWHG JURXS ,Q D VLPLODU IDVKLRQ WKH ZRUG DQG ZRUG /LQHDU :UDS PRGHV EHJLQ WKHLU EXUVW VHTXHQFH RQ WKH VWDUWLQJ DGGUHVV ZULWWHQ WR WKH GHYLFH DQG WKHQ ZUDS EDFN WR WKH ILUVW DGGUHVV LQ WKH VHOHFWHG DGGUHVV JURXS 1RWH WKDW LQ WKHVH WKUHH EXUVW UHDG PRGHV WKH DGGUHVV SRLQWHU GRHV QRW FURVV WKH ERXQGDU\ WKDW RFFXUV HYHU\ RU ZRUGV WKXV QR ZDLW VWDWHV DUH LQVHUWHG H[FHSW GXULQJ WKH LQLWLDO DFFHVV 7KH 5'< SLQ LQGLFDWHV ZKHQ GDWD LV YDOLG RQ WKH EXV
Configuration Register
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Handshaking
7KH GHYLFH LV HTXLSSHG ZLWK D KDQGVKDNLQJ IHDWXUH WKDW DOORZV WKH KRVW V\VWHP WR VLPSO\ PRQLWRU WKH 5'< VLJQDO IURP WKH GHYLFH WR GHWHUPLQH ZKHQ WKH LQLWLDO ZRUG RI EXUVW GDWD LV UHDG\ WR EH UHDG 7KH KRVW V\VWHP VKRXOG XVH WKH SURJUDP PDEOH ZDLW VWDWH FRQILJXUDWLRQ WR VHW WKH QXPEHU RI ZDLW VWDWHV IRU RSWLPDO EXUVW PRGH RSHUDWLRQ 7KH LQLWLDO ZRUG RI EXUVW GDWD LV LQGLFDWHG E\ WKH DFWLYH HGJH RI 5'< DIWHU 2( JRHV ORZ )RU RSWLPDO EXUVW PRGH SHUIRUPDQFH WKH KRVW V\VWHP PXVW VHW WKH DSSURSULDWH QXPEHU RI ZDLW VWDWHV LQ WKH IODVK GHYLFH GHSHQGLQJ RQ FORFN IUHTXHQF\ 6HH 6HW &RQILJXUDWLRQ 5HJLVWHU &RPPDQG 6HTXHQFH VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
27
Preliminary
Simultaneous Read/Write Operations with Zero Latency
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Writing Commands/Command Sequences
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Accelerated Program Operation
7KH GHYLFH RIIHUV DFFHOHUDWHG SURJUDP RSHUDWLRQV WKURXJK WKH $&& IXQFWLRQ $&& LV SULPDULO\ LQWHQGHG WR DOORZ IDVWHU PDQXIDFWXULQJ WKURXJKSXW DW WKH IDFWRU\ ,I WKH V\VWHP DVVHUWV 9++ RQ WKLV LQSXW WKH GHYLFH DXWRPDWLFDOO\ HQWHUV WKH DIRUH PHQWLRQHG 8QORFN %\SDVV PRGH DQG XVHV WKH KLJKHU YROWDJH RQ WKH LQSXW WR UHGXFH WKH WLPH UHTXLUHG IRU SURJUDP RSHUDWLRQV 7KH V\VWHP ZRXOG XVH D WZR F\FOH SURJUDP FRPPDQG VHTXHQFH DV UHTXLUHG E\ WKH 8QORFN %\SDVV PRGH 5H PRYLQJ 9++ IURP WKH $&& LQSXW UHWXUQV WKH GHYLFH WR QRUPDO RSHUDWLRQ 1RWH WKDW VHFWRUV PXVW EH XQORFNHG SULRU WR UDLVLQJ $&& WR 9++ 1RWH WKDW WKH $&& SLQ PXVW QRW EH DW 9++ IRU RSHUDWLRQV RWKHU WKDQ DFFHOHUDWHG SURJUDPPLQJ RU GHYLFH GDP
28
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
DJH PD\ UHVXOW ,Q DGGLWLRQ WKH $&& SLQ PXVW QRW EH OHIW IORDWLQJ RU XQFRQQHFWHG LQFRQVLVWHQW EHKDYLRU RI WKH GHYLFH PD\ UHVXOW :KHQ DW 9,/ $&& ORFNV DOO VHFWRUV $&& VKRXOG EH DW 9,+ IRU DOO RWKHU FRQGLWLRQV
Autoselect Mode
7KH DXWRVHOHFW PRGH SURYLGHV PDQXIDFWXUHU DQG GHYLFH LGHQWLILFDWLRQ DQG VHF WRU SURWHFWLRQ YHULILFDWLRQ WKURXJK LGHQWLILHU FRGHV RXWSXW IURP WKH LQWHUQDO UHJLVWHU ZKLFK LV VHSDUDWH IURP WKH PHPRU\ DUUD\ RQ '4'4 7KLV PRGH LV SULPDULO\ LQWHQGHG IRU SURJUDPPLQJ HTXLSPHQW WR DXWRPDWLFDOO\ PDWFK D GHYLFH WR EH SURJUDPPHG ZLWK LWV FRUUHVSRQGLQJ SURJUDPPLQJ DOJRULWKP +RZHYHU WKH DXWRVHOHFW FRGHV FDQ DOVR EH DFFHVVHG LQV\VWHP WKURXJK WKH FRPPDQG UHJLVWHU :KHQ XVLQJ SURJUDPPLQJ HTXLSPHQW WKH DXWRVHOHFW PRGH UHTXLUHV 9,' RQ DG GUHVV SLQ $ $GGUHVV SLQV PXVW EH DV VKRZQ LQ 7DEOH $XWRVHOHFW &RGHV +LJK 9ROWDJH 0HWKRG RQ SDJH ,Q DGGLWLRQ ZKHQ YHULI\LQJ VHFWRU SURWHFWLRQ WKH VHFWRU DGGUHVV PXVW DSSHDU RQ WKH DSSURSULDWH KLJKHVW RUGHU DGGUHVV ELWV VHH 7DEOH 6:6-B0&3 %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHF WLRQ8QSURWHFWLRQ RQ SDJH DQG 7DEOH 6:6- %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSURWHFWLRQ RQ SDJH 7DEOH VKRZV WKH UHPDLQLQJ DGGUHVV ELWV WKDW DUH GRQW FDUH :KHQ DOO QHFHVVDU\ ELWV KDYH EHHQ VHW DV UHTXLUHG WKH SURJUDPPLQJ HTXLSPHQW PD\ WKHQ UHDG WKH FRUUHVSRQGLQJ LGHQWLILHU FRGH RQ '4'4 +RZHYHU WKH DXWRVHOHFW FRGHV FDQ DOVR EH DF FHVVHG LQV\VWHP WKURXJK WKH FRPPDQG UHJLVWHU IRU LQVWDQFHV ZKHQ WKH GHYLFH LV HUDVHG RU SURJUDPPHG LQ D V\VWHP ZLWKRXW DFFHVV WR KLJK YROWDJH RQ WKH $ SLQ 7KH FRPPDQG VHTXHQFH LV LOOXVWUDWHG LQ 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH 1RWH WKDW LI D %DQN $GGUHVV %$ RQ DGGUHVV ELWV $ $ DQG $ IRU WKH :6- $$ IRU WKH :6- LV DVVHUWHG GXULQJ WKH WKLUG ZULWH F\FOH RI WKH DXWRVHOHFW FRPPDQG WKH KRVW V\VWHP FDQ UHDG DXWRVHOHFW GDWD WKDW EDQN DQG WKHQ LPPHGLDWHO\ UHDG DUUD\ GDWD IURP WKH RWKHU EDQN ZLWKRXW H[LWLQJ WKH DXWRVHOHFW PRGH 7R DFFHVV WKH DXWRVHOHFW FRGHV LQV\VWHP WKH KRVW V\VWHP FDQ LVVXH WKH DXWRVH OHFW FRPPDQG YLD WKH FRPPDQG UHJLVWHU DV VKRZQ LQ 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH 7KLV PHWKRG GRHV QRW UHTXLUH 9,' $XWRVHOHFW PRGH PD\ RQO\ EH HQWHUHG DQG XVHG ZKHQ LQ WKH DV\QFKURQRXV UHDG PRGH 5HIHU WR WKH $XWRVHOHFW &RPPDQG 6HTXHQFH VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
29
Preliminary
Table 3. Autoselect Codes (High Voltage Method)
$PD [ WR $ ; $ WR $ $ $ $ ; 9,' ; ; $ WR $ $ $ $ $ $ / ; / / / / + + ; ; 9,' ; / / / + + / / + + 6$ ; 9,' ; / / / / / / + + / / / + + + / + / + /
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+
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Sector/Sector Block Protection and Unprotection
7KH KDUGZDUH VHFWRU SURWHFWLRQ IHDWXUH GLVDEOHV ERWK SURJUDPPLQJ DQG HUDVH RS HUDWLRQV LQ DQ\ VHFWRU 7KH KDUGZDUH VHFWRU XQSURWHFWLRQ IHDWXUH UHHQDEOHV ERWK SURJUDP DQG HUDVH RSHUDWLRQV LQ SUHYLRXVO\ SURWHFWHG VHFWRUV 6HFWRU SURWHFWLRQ XQSURWHFWLRQ FDQ EH LPSOHPHQWHG YLD WZR PHWKRGV 1RWH )RU WKH IROORZLQJ GLVFXVVLRQ WKH WHUP VHFWRU DSSOLHV WR ERWK VHFWRUV DQG VHFWRU EORFNV $ VHFWRU EORFN FRQVLVWV RI WZR RU PRUH DGMDFHQW VHFWRUV WKDW DUH SURWHFWHG RU XQSURWHFWHG DW WKH VDPH WLPH VHH 7DEOH 6:6-B0&3 %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSURWHFWLRQ RQ SDJH DQG 7DEOH 6:6- %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSUR WHFWLRQ RQ SDJH
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protection/Unprotection
6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ $$ 6HFWRU 6HFWRU %ORFN 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV
30
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
6HFWRU 6$ 6$ 6$ 6$ 6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$
$$ ;;; ;;; ;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;;
6HFWRU 6HFWRU %ORFN 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
31
Preliminary
6HFWRU 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
$$ ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;; ;;; ;;;
6HFWRU 6HFWRU %ORFN 6L]H [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV
Table 5.
S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection
6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ $$ ;;; 6HFWRU 6HFWRU %ORFN 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV
32
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
6HFWRU 6$ 6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
$$ ;;; ;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;; ;;; ;;;
6HFWRU 6HFWRU %ORFN 6L]H .ZRUGV .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV [ .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
33
Preliminary 6HFWRU 3URWHFWLRQ
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Persistent Sector Protection
7KH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ PHWKRG UHSODFHV WKH ROG 9 FRQWUROOHG SURWHF WLRQ PHWKRG ZKLOH DW WKH VDPH WLPH HQKDQFLQJ IOH[LELOLW\ E\ SURYLGLQJ WKUHH GLIIHUHQW VHFWRU SURWHFWLRQ VWDWHV 3HUVLVWHQWO\ /RFNHG$ VHFWRU LV SURWHFWHG DQG FDQQRW EH FKDQJHG '\QDPLFDOO\ /RFNHG7KH VHFWRU LV SURWHFWHG DQG FDQ EH FKDQJHG E\ D VLP SOH FRPPDQG 8QORFNHG7KH VHFWRU LV XQSURWHFWHG DQG FDQ EH FKDQJHG E\ D VLPSOH FRP PDQG ,Q RUGHU WR DFKLHYH WKHVH VWDWHV WKUHH W\SHV RI ELWV DUH JRLQJ WR EH XVHG
34
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary 3HUVLVWHQW 3URWHFWLRQ %LW 33%
$ VLQJOH 3HUVLVWHQW QRQYRODWLOH 3URWHFWLRQ %LW LV DVVLJQHG WR D PD[LPXP RI IRXU VHFWRUV 6:6-B0&3 %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHF WLRQ8QSURWHFWLRQ VHFWLRQ RQ SDJH 6:6- %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSURWHFWLRQ VHFWLRQ RQ SDJH $OO .E\WH ERRW EORFN VHFWRUV KDYH LQGLYLGXDO VHFWRU 3HUVLVWHQW 3URWHFWLRQ %LWV 33%V IRU JUHDWHU IOH[LELOLW\ (DFK 33% LV LQGLYLGXDOO\ PRGLILDEOH WKURXJK WKH 33% 3URJUDP &RPPDQG 1RWH ,I D 33% UHTXLUHV HUDVXUH DOO RI WKH VHFWRU 33%V PXVW ILUVW EH SUHSUR JUDPPHG SULRU WR 33% HUDVLQJ $OO 33%V HUDVH LQ SDUDOOHO XQOLNH SURJUDPPLQJ ZKHUH LQGLYLGXDO 33%V DUH SURJUDPPDEOH ,W LV WKH UHVSRQVLELOLW\ RI WKH XVHU WR SHUIRUP WKH SUHSURJUDPPLQJ RSHUDWLRQ 2WKHUZLVH DQ DOUHDG\ HUDVHG VHFWRU 33%V KDV WKH SRWHQWLDO RI EHLQJ RYHUHUDVHG 7KHUH LV QR KDUGZDUH PHFKDQLVP WR SUHYHQW VHFWRU 33%V RYHUHUDVXUH
3HUVLVWHQW 3URWHFWLRQ %LW /RFN 33% /RFN
$ JOREDO YRODWLOH ELW :KHQ VHW WR WKH 33%V FDQQRW EH FKDQJHG :KHQ FOHDUHG WKH 33%V DUH FKDQJHDEOH 7KHUH LV RQO\ RQH 33% /RFN ELW SHU GHYLFH 7KH 33% /RFN LV FOHDUHG DIWHU SRZHUXS RU KDUGZDUH UHVHW 7KHUH LV QR FRPPDQG VH TXHQFH WR XQORFN WKH 33% /RFN
'\QDPLF 3URWHFWLRQ %LW '<%
$ YRODWLOH SURWHFWLRQ ELW LV DVVLJQHG IRU HDFK VHFWRU $IWHU SRZHUXS RU KDUGZDUH UHVHW WKH FRQWHQWV RI DOO '<%V LV (DFK '<% LV LQGLYLGXDOO\ PRGLILDEOH WKURXJK WKH '3% :ULWH &RPPDQG :KHQ WKH SDUWV DUH ILUVW VKLSSHG WKH 33%V DUH FOHDUHG 7KH '3%V DQG 33% /RFN DUH GHIDXOWHG WR SRZHU XS LQ WKH FOHDUHG VWDWH PHDQLQJ WKH 33%V DUH FKDQJHDEOH :KHQ WKH GHYLFH LV ILUVW SRZHUHG RQ WKH '<%V SRZHU XS LQ WKH FOHDUHG VWDWH VHFWRUV QRW SURWHFWHG 7KH 3URWHFWLRQ 6WDWH IRU HDFK VHFWRU LV GHWHUPLQHG E\ WKH ORJLFDO 25 RI WKH 33% DQG WKH '3% UHODWHG WR WKDW VHFWRU )RU WKH VHFWRUV WKDW KDYH WKH 33%V FOHDUHG WKH '3%V FRQWURO ZKHWKHU RU QRW WKH VHFWRU LV SURWHFWHG RU XQSURWHFWHG %\ LVVXLQJ WKH '3% :ULWH FRPPDQG VHTXHQFHV WKH '3%V ZLOO EH VHW RU FOHDUHG WKXV SODFLQJ HDFK VHFWRU LQ WKH SURWHFWHG RU XQSURWHFWHG VWDWH 7KHVH DUH WKH VRFDOOHG '\QDPLF /RFNHG RU 8QORFNHG VWDWHV 7KH\ DUH FDOOHG G\QDPLF VWDWHV EHFDXVH LW LV YHU\ HDV\ WR VZLWFK EDFN DQG IRUWK EHWZHHQ WKH SURWHFWHG DQG XQSURWHFWHG FRQGLWLRQV 7KLV DOORZV VRIWZDUH WR HDVLO\ SURWHFW VHF WRUV DJDLQVW LQDGYHUWHQW FKDQJHV \HW GRHV QRW SUHYHQW WKH HDV\ UHPRYDO RI SURWHFWLRQ ZKHQ FKDQJHV DUH QHHGHG 7KH '3%V PD\EH VHW RU FOHDUHG DV RIWHQ DV QHHGHG 7KH 33%V DOORZ IRU D PRUH VWDWLF DQG GLIILFXOW WR FKDQJH OHYHO RI SURWHFWLRQ 7KH 33%V UHWDLQ WKHLU VWDWH DFURVV SRZHU F\FOHV EHFDXVH WKH\ DUH 1RQ9RODWLOH ,QGL YLGXDO 33%V DUH VHW ZLWK D FRPPDQG EXW PXVW DOO EH FOHDUHG DV D JURXS WKURXJK D FRPSOH[ VHTXHQFH RI SURJUDP DQG HUDVLQJ FRPPDQGV 7KH 33%V DUH DOVR OLP LWHG WR HUDVH F\FOHV 7KH 3%% /RFN ELW DGGV DQ DGGLWLRQDO OHYHO RI SURWHFWLRQ 2QFH DOO 33%V DUH SUR JUDPPHG WR WKH GHVLUHG VHWWLQJV WKH 33% /RFN PD\ EH VHW WR 6HWWLQJ WKH 33% /RFN GLVDEOHV DOO SURJUDP DQG HUDVH FRPPDQGV WR WKH 1RQ9RODWLOH 33%V ,Q HIIHFW WKH 33% /RFN %LW ORFNV WKH 33%V LQWR WKHLU FXUUHQW VWDWH 7KH RQO\ ZD\ WR FOHDU WKH 33% /RFN LV WR JR WKURXJK D SRZHU F\FOH 6\VWHP ERRW FRGH FDQ GHWHU PLQH LI DQ\ FKDQJHV WR WKH 33% DUH QHHGHG HJ WR DOORZ QHZ V\VWHP FRGH WR EH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
35
Preliminary
GRZQORDGHG ,I QR FKDQJHV DUH QHHGHG WKHQ WKH ERRW FRGH FDQ VHW WKH 33% /RFN WR GLVDEOH DQ\ IXUWKHU FKDQJHV WR WKH 33%V GXULQJ V\VWHP RSHUDWLRQ 7KH :3 ZULWH SURWHFW SLQ DGGV D ILQDO OHYHO RI KDUGZDUH SURWHFWLRQ WR WKH IRXU RXWHUPRVW .E\WHV VHFWRUV 6$ 6$ IRU D ERWWRP ERRW :6- 6$ 6$ :6- 6$ 6$ RU 6$ 6$ :6- 6$ 6$ :6- 6$ 6$ IRU D GXDO ERRW :KHQ WKLV SLQ LV ORZ LW LV QRW SRVVLEOH WR FKDQJH WKH FRQWHQWV RI WKHVH IRXU VHFWRUV 7KHVH VHFWRUV JHQHUDOO\ KROG V\V WHP ERRW FRGH 6R WKH :3 SLQ FDQ SUHYHQW DQ\ FKDQJHV WR WKH ERRW FRGH WKDW FRXOG RYHUULGH WKH FKRLFHV PDGH ZKLOH VHWWLQJ XS VHFWRU SURWHFWLRQ GXULQJ V\V WHP LQLWLDOL]DWLRQ ,W LV SRVVLEOH WR KDYH VHFWRUV WKDW KDYH EHHQ SHUVLVWHQWO\ ORFNHG DQG VHFWRUV WKDW DUH OHIW LQ WKH G\QDPLF VWDWH 7KH VHFWRUV LQ WKH G\QDPLF VWDWH DUH DOO XQ SURWHFWHG ,I WKHUH LV D QHHG WR SURWHFW VRPH RI WKHP D VLPSOH '3% :ULWH FRPPDQG VHTXHQFH LV DOO WKDW LV QHFHVVDU\ 7KH '3% ZULWH FRPPDQG IRU WKH G\ QDPLF VHFWRUV VZLWFK WKH '3%V WR VLJQLI\ SURWHFWHG DQG XQSURWHFWHG UHVSHFWLYHO\ ,I WKHUH LV D QHHG WR FKDQJH WKH VWDWXV RI WKH SHUVLVWHQWO\ ORFNHG VHFWRUV D IHZ PRUH VWHSV DUH UHTXLUHG )LUVW WKH 33% /RFN ELW PXVW EH GLVDEOHG E\ HLWKHU SXWWLQJ WKH GHYLFH WKURXJK D SRZHUF\FOH RU KDUGZDUH UHVHW 7KH 33%V FDQ WKHQ EH FKDQJHG WR UHIOHFW WKH GHVLUHG VHWWLQJV 6HWWLQJ WKH 33% ORFN ELW RQFH DJDLQ ZLOO ORFN WKH 33%V DQG WKH GHYLFH RSHUDWHV QRUPDOO\ DJDLQ 1RWH WR DFKLHYH WKH EHVW SURWHFWLRQ LWV UHFRPPHQGHG WR H[HFXWH WKH 33% ORFN ELW VHW FRPPDQG HDUO\ LQ WKH ERRW FRGH DQG SURWHFW WKH ERRW FRGH E\ KROGLQJ :3 9,/
Table 6. Sector Protection Schemes
'3% 33% 33% /RFN 6HFWRU 6WDWH 8QSURWHFWHG33% DQG '3% DUH FKDQJHDEOH 3URWHFWHG33% DQG '3% DUH FKDQJHDEOH 3URWHFWHG33% DQG '3% DUH FKDQJHDEOH 3URWHFWHG33% DQG '3% DUH FKDQJHDEOH 8QSURWHFWHG33% QRW FKDQJHDEOH '3% LV FKDQJHDEOH 3URWHFWHG33% QRW FKDQJHDEOH '3% LV FKDQJHDEOH 3URWHFWHG33% QRW FKDQJHDEOH '3% LV FKDQJHDEOH 3URWHFWHG33% QRW FKDQJHDEOH '3% LV FKDQJHDEOH
7DEOH FRQWDLQV DOO SRVVLEOH FRPELQDWLRQV RI WKH '3% 33% DQG 33% ORFN UHODWLQJ WR WKH VWDWXV RI WKH VHFWRU ,Q VXPPDU\ LI WKH 33% LV VHW DQG WKH 33% ORFN LV VHW WKH VHFWRU LV SURWHFWHG DQG WKH SURWHFWLRQ FDQ QRW EH UHPRYHG XQWLO WKH QH[W SRZHU F\FOH FOHDUV WKH 33% ORFN ,I WKH 33% LV FOHDUHG WKH VHFWRU FDQ EH G\QDPLFDOO\ ORFNHG RU XQORFNHG 7KH '3% WKHQ FRQWUROV ZKHWKHU RU QRW WKH VHFWRU LV SURWHFWHG RU XQSURWHFWHG
36
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
,I WKH XVHU DWWHPSWV WR SURJUDP RU HUDVH D SURWHFWHG VHFWRU WKH GHYLFH LJQRUHV WKH FRPPDQG DQG UHWXUQV WR UHDG PRGH $ SURJUDP FRPPDQG WR D SURWHFWHG VHFWRU HQDEOHV VWDWXV SROOLQJ IRU DSSUR[LPDWHO\ V EHIRUH WKH GHYLFH UHWXUQV WR UHDG PRGH ZLWKRXW KDYLQJ PRGLILHG WKH FRQWHQWV RI WKH SURWHFWHG VHFWRU $Q HUDVH FRPPDQG WR D SURWHFWHG VHFWRU HQDEOHV VWDWXV SROOLQJ IRU DSSUR[LPDWHO\ V DIWHU ZKLFK WKH GHYLFH UHWXUQV WR UHDG PRGH ZLWKRXW KDYLQJ HUDVHG WKH SURWHFWHG VHFWRU 7KH SURJUDPPLQJ RI WKH '3% 33% DQG 33% ORFN IRU D JLYHQ VHFWRU FDQ EH YHUL ILHG E\ ZULWLQJ D '3%33%33% ORFN YHULI\ FRPPDQG WR WKH GHYLFH
Persistent Sector Protection Mode Locking Bit
/LNH WKH SDVVZRUG PRGH ORFNLQJ ELW D 3HUVLVWHQW 6HFWRU 3URWHFWLRQ PRGH ORFNLQJ ELW H[LVWV WR JXDUDQWHH WKDW WKH GHYLFH UHPDLQ LQ VRIWZDUH VHFWRU SURWHFWLRQ 2QFH VHW WKH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ ORFNLQJ ELW SUHYHQWV SURJUDPPLQJ RI WKH SDVVZRUG SURWHFWLRQ PRGH ORFNLQJ ELW 7KLV JXDUDQWHHV WKDW D KDFNHU FRXOG QRW SODFH WKH GHYLFH LQ SDVVZRUG SURWHFWLRQ PRGH
Password Protection Mode
7KH 3DVVZRUG 6HFWRU 3URWHFWLRQ 0RGH PHWKRG DOORZV DQ HYHQ KLJKHU OHYHO RI VH FXULW\ WKDQ WKH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ 0RGH 7KHUH DUH WZR PDLQ GLIIHUHQFHV EHWZHHQ WKH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ DQG WKH 3DVVZRUG 6HFWRU 3URWHFWLRQ 0RGH :KHQ WKH GHYLFH LV ILUVW SRZHUHG RQ RU FRPHV RXW RI D UHVHW F\FOH WKH 33% /RFN ELW LV VHW WR WKH ORFNHG VWDWH UDWKHU WKDQ FOHDUHG WR WKH XQORFNHG VWDWH 7KH RQO\ PHDQV WR FOHDU WKH 33% /RFN ELW LV E\ ZULWLQJ D XQLTXH ELW 3DVV ZRUG WR WKH GHYLFH 7KH 3DVVZRUG 6HFWRU 3URWHFWLRQ PHWKRG LV RWKHUZLVH LGHQWLFDO WR WKH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ PHWKRG $ ELW SDVVZRUG LV WKH RQO\ DGGLWLRQDO WRRO XWLOL]HG LQ WKLV PHWKRG 7KH SDVVZRUG LV VWRUHG LQ D WKH 6HFXUHG 6LOLFRQ UHJLRQ RI WKH IODVK PHPRU\ 2QFH WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV VHW WKH SDVVZRUG LV SHUPDQHQWO\ VHW ZLWK QR PHDQV WR UHDG SURJUDP RU HUDVH LW 7KH SDVVZRUG LV XVHG WR FOHDU WKH 33% /RFN ELW 7KH 3DVVZRUG 8QORFN FRPPDQG PXVW EH ZULWWHQ WR WKH IODVK DORQJ ZLWK D SDVVZRUG 7KH IODVK GHYLFH LQWHUQDOO\ FRPSDUHV WKH JLYHQ SDVVZRUG ZLWK WKH SUHSURJUDPPHG SDVVZRUG ,I WKH\ PDWFK WKH 33% /RFN ELW LV FOHDUHG DQG WKH 33%V FDQ EH DOWHUHG ,I WKH\ GR QRW PDWFK WKH IODVK GHYLFH GRHV QRWKLQJ 7KHUH LV D EXLOWLQ V GHOD\ IRU HDFK SDVVZRUG FKHFN 7KLV GHOD\ LV LQWHQGHG WR WKZDUW DQ\ HIIRUWV WR UXQ D SURJUDP WKDW WULHV DOO SRVVLEOH FRPELQDWLRQV LQ RUGHU WR FUDFN WKH SDVVZRUG
Password and Password Mode Locking Bit
,Q RUGHU WR VHOHFW WKH 3DVVZRUG VHFWRU SURWHFWLRQ VFKHPH WKH FXVWRPHU PXVW ILUVW SURJUDP WKH SDVVZRUG )$6/ UHFRPPHQGV WKDW WKH SDVVZRUG EH VRPHKRZ FRUUH ODWHG WR WKH XQLTXH (OHFWURQLF 6HULDO 1XPEHU (61 RI WKH SDUWLFXODU IODVK GHYLFH (DFK (61 LV GLIIHUHQW IRU HYHU\ IODVK GHYLFH WKHUHIRUH HDFK SDVVZRUG VKRXOG EH GLIIHUHQW IRU HYHU\ IODVK GHYLFH :KLOH SURJUDPPLQJ LQ WKH SDVVZRUG UHJLRQ WKH FXVWRPHU PD\ SHUIRUP 3DVVZRUG 9HULI\ RSHUDWLRQV 2QFH WKH GHVLUHG SDVVZRUG LV SURJUDPPHG LQ WKH FXVWRPHU PXVW WKHQ VHW WKH 3DVVZRUG 0RGH /RFNLQJ %LW 7KLV RSHUDWLRQ DFKLHYHV WZR REMHFWLYHV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
37
Preliminary
,W SHUPDQHQWO\ VHWV WKH GHYLFH WR RSHUDWH XVLQJ WKH 3DVVZRUG 3URWHFWLRQ 0RGH ,W LV QRW SRVVLEOH WR UHYHUVH WKLV IXQFWLRQ ,W DOVR GLVDEOHV DOO IXUWKHU FRPPDQGV WR WKH SDVVZRUG UHJLRQ $OO SURJUDP DQG UHDG RSHUDWLRQV DUH LJQRUHG %RWK RI WKHVH REMHFWLYHV DUH LPSRUWDQW DQG LI QRW FDUHIXOO\ FRQVLGHUHG PD\ OHDG WR XQUHFRYHUDEOH HUURUV 7KH XVHU PXVW EH VXUH WKDW WKH 3DVVZRUG 3URWHFWLRQ PHWKRG LV GHVLUHG ZKHQ VHWWLQJ WKH 3DVVZRUG 0RGH /RFNLQJ %LW 0RUH LPSRU WDQWO\ WKH XVHU PXVW EH VXUH WKDW WKH SDVVZRUG LV FRUUHFW ZKHQ WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV VHW 'XH WR WKH IDFW WKDW UHDG RSHUDWLRQV DUH GLVDEOHG WKHUH LV QR PHDQV WR YHULI\ ZKDW WKH SDVVZRUG LV DIWHUZDUGV ,I WKH SDVVZRUG LV ORVW DIWHU VHWWLQJ WKH 3DVVZRUG 0RGH /RFNLQJ %LW WKHUH ZLOO EH QR ZD\ WR FOHDU WKH 33% /RFN ELW 7KH 3DVVZRUG 0RGH /RFNLQJ %LW RQFH VHW SUHYHQWV UHDGLQJ WKH ELW SDVVZRUG RQ WKH '4 EXV DQG IXUWKHU SDVVZRUG SURJUDPPLQJ 7KH 3DVVZRUG 0RGH /RFNLQJ %LW LV QRW HUDVDEOH 2QFH 3DVVZRUG 0RGH /RFNLQJ %LW LV SURJUDPPHG WKH 3HUVLV WHQW 6HFWRU 3URWHFWLRQ /RFNLQJ %LW LV GLVDEOHG IURP SURJUDPPLQJ JXDUDQWHHLQJ WKDW QR FKDQJHV WR WKH SURWHFWLRQ VFKHPH DUH DOORZHG
64-bit Password
7KH ELW 3DVVZRUG LV ORFDWHG LQ LWV RZQ PHPRU\ VSDFH DQG LV DFFHVVLEOH WKURXJK WKH XVH RI WKH 3DVVZRUG 3URJUDP DQG 9HULI\ FRPPDQGV VHH 3DVVZRUG 3URJUDP &RPPDQG VHFWLRQ RQ SDJH DQG 3DVVZRUG 9HULI\ &RPPDQG VHF WLRQ RQ SDJH 7KH SDVVZRUG IXQFWLRQ ZRUNV LQ FRQMXQFWLRQ ZLWK WKH 3DVVZRUG 0RGH /RFNLQJ %LW ZKLFK ZKHQ VHW SUHYHQWV WKH 3DVVZRUG 9HULI\ FRPPDQG IURP UHDGLQJ WKH FRQWHQWV RI WKH SDVVZRUG RQ WKH SLQV RI WKH GHYLFH
Persistent Protection Bit Lock
7KH 3HUVLVWHQW 3URWHFWLRQ %LW 33% /RFN LV D YRODWLOH ELW WKDW UHIOHFWV WKH VWDWH RI WKH 3DVVZRUG 0RGH /RFNLQJ %LW DIWHU SRZHUXS UHVHW ,I WKH 3DVVZRUG 0RGH /RFN %LW LV DOVR VHW DIWHU D KDUGZDUH UHVHW 5(6(7 DVVHUWHG RU D SRZHUXS UHVHW WKH 21/< PHDQV IRU FOHDULQJ WKH 33% /RFN %LW LQ 3DVVZRUG 3URWHFWLRQ 0RGH LV WR LVVXH WKH 3DVVZRUG 8QORFN FRPPDQG 6XFFHVVIXO H[HFXWLRQ RI WKH 3DVVZRUG 8Q ORFN FRPPDQG FOHDUV WKH 33% /RFN %LW DOORZLQJ IRU VHFWRU 33%V PRGLILFDWLRQV $VVHUWLQJ 5(6(7 WDNLQJ WKH GHYLFH WKURXJK D SRZHURQ UHVHW RU LVVXLQJ WKH 33% /RFN %LW 6HW FRPPDQG VHWV WKH 33% /RFN %LW WR D ,I WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV QRW VHW LQFOXGLQJ 3HUVLVWHQW 3URWHFWLRQ 0RGH WKH 33% /RFN %LW LV FOHDUHG DIWHU SRZHUXS RU KDUGZDUH UHVHW 7KH 33% /RFN %LW LV VHWDEOH E\ LVVXLQJ WKH 33% /RFN %LW 6HW FRPPDQG 2QFH VHW WKH RQO\ PHDQV IRU FOHDULQJ WKH 33% /RFN %LW LV E\ LVVXLQJ D KDUGZDUH RU SRZHUXS UHVHW 7KH 3DVVZRUG 8QORFN FRPPDQG LV LJQRUHG LQ 3HUVLVWHQW 3URWHFWLRQ 0RGH
+LJK 9ROWDJH 6HFWRU 3URWHFWLRQ
6HFWRU SURWHFWLRQ DQG XQSURWHFWLRQ PD\ DOVR EH LPSOHPHQWHG XVLQJ SURJUDPPLQJ HTXLSPHQW 7KH SURFHGXUH UHTXLUHV KLJK YROWDJH 9,' WR EH SODFHG RQ WKH 5( 6(7 SLQ 5HIHU WR )LJXUH ,Q6\VWHP 6HFWRU 3URWHFWLRQ6HFWRU 8QSURWHFWLRQ $OJRULWKPV RQ SDJH IRU GHWDLOV RQ WKLV SURFHGXUH 1RWH WKDW IRU VHFWRU XQSUR WHFW DOO XQSURWHFWHG VHFWRUV PXVW EH ILUVW SURWHFWHG SULRU WR WKH ILUVW VHFWRU ZULWH F\FOH 2QFH WKH 3DVVZRUG 0RGH /RFNLQJ ELW RU 3HUVLVWHQW 3URWHFWLRQ /RFNLQJ ELW DUH VHW WKH KLJK YROWDJH VHFWRU SURWHFWXQSURWHFW FDSDELOLW\ LV GLVDEOHG
38
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Standby Mode
:KHQ WKH V\VWHP LV QRW UHDGLQJ RU ZULWLQJ WR WKH GHYLFH LW FDQ SODFH WKH GHYLFH LQ WKH VWDQGE\ PRGH ,Q WKLV PRGH FXUUHQW FRQVXPSWLRQ LV JUHDWO\ UHGXFHG DQG WKH RXWSXWV DUH SODFHG LQ WKH KLJK LPSHGDQFH VWDWH LQGHSHQGHQW RI WKH 2( LQSXW 7KH GHYLFH HQWHUV WKH &026 VWDQGE\ PRGH ZKHQ WKH &( DQG 5(6(7 LQSXWV DUH ERWK KHOG DW 9&& 9 7KH GHYLFH UHTXLUHV VWDQGDUG DFFHVV WLPH W&( IRU UHDG DFFHVV EHIRUH LW LV UHDG\ WR UHDG GDWD ,I WKH GHYLFH LV GHVHOHFWHG GXULQJ HUDVXUH RU SURJUDPPLQJ WKH GHYLFH GUDZV DF WLYH FXUUHQW XQWLO WKH RSHUDWLRQ LV FRPSOHWHG ,&& LQ WKH '& &KDUDFWHULVWLFV VHFWLRQ RQ SDJH UHSUHVHQWV WKH VWDQGE\ FXU UHQW VSHFLILFDWLRQ
Automatic Sleep Mode
7KH DXWRPDWLF VOHHS PRGH PLQLPL]HV )ODVK GHYLFH HQHUJ\ FRQVXPSWLRQ :KLOH LQ DV\QFKURQRXV PRGH WKH GHYLFH DXWRPDWLFDOO\ HQDEOHV WKLV PRGH ZKHQ DGGUHVVHV UHPDLQ VWDEOH IRU W$&& QV 7KH DXWRPDWLF VOHHS PRGH LV LQGHSHQGHQW RI WKH &( :( DQG 2( FRQWURO VLJQDOV 6WDQGDUG DGGUHVV DFFHVV WLPLQJV SURYLGH QHZ GDWD ZKHQ DGGUHVVHV DUH FKDQJHG :KLOH LQ VOHHS PRGH RXWSXW GDWD LV ODWFKHG DQG DOZD\V DYDLODEOH WR WKH V\VWHP %DVHG RQ WKH LPSOHPHQWDWLRQ E\ GHVLJQ WKH $XWR 3RZHU 'RZQ IHDWXUH LV GLVDEOHG LQ V\QFKURQRXV PRGH DQG HQDEOHG LQ DV\QFKURQRXV PRGH $V D UHVXOW LQ V\QFKURQRXV PRGH WKH GHYLFH FDQ EH LQ $XWR 3RZHU 'RZQ 0RGH RQO\ E\ GHVHOHFWLQJ WKH &( 1RWH WKDW D QHZ EXUVW RSHUDWLRQ LV UHTXLUHG WR SURYLGH QHZ GDWD ,&& LQ WKH '& &KDUDFWHULVWLFV VHFWLRQ RQ SDJH UHSUHVHQWV WKH DXWRPDWLF VOHHS PRGH FXUUHQW VSHFLILFDWLRQ
5(6(7 +DUGZDUH 5HVHW ,QSXW
7KH 5(6(7 LQSXW SURYLGHV D KDUGZDUH PHWKRG RI UHVHWWLQJ WKH GHYLFH WR UHDGLQJ DUUD\ GDWD :KHQ 5(6(7 LV GULYHQ ORZ IRU DW OHDVW D SHULRG RI W53 WKH GHYLFH LP PHGLDWHO\ WHUPLQDWHV DQ\ RSHUDWLRQ LQ SURJUHVV WULVWDWHV DOO RXWSXWV UHVHWV WKH FRQILJXUDWLRQ UHJLVWHU DQG LJQRUHV DOO UHDGZULWH FRPPDQGV IRU WKH GXUDWLRQ RI WKH 5(6(7 SXOVH 7KH GHYLFH DOVR UHVHWV WKH LQWHUQDO VWDWH PDFKLQH WR UHDGLQJ DUUD\ GDWD 7KH RSHUDWLRQ WKDW ZDV LQWHUUXSWHG VKRXOG EH UHLQLWLDWHG RQFH WKH GH YLFH LV UHDG\ WR DFFHSW DQRWKHU FRPPDQG VHTXHQFH WR HQVXUH GDWD LQWHJULW\ &XUUHQW LV UHGXFHG IRU WKH GXUDWLRQ RI WKH 5(6(7 SXOVH :KHQ 5(6(7 DW 966 9 WKH GHYLFH GUDZV &026 VWDQGE\ FXUUHQW ,&& ,I 5(6(7 DW 9,/ EXW QRW ZLWKLQ 966 9 WKH VWDQGE\ FXUUHQW ZLOO EH JUHDWHU LV KHOG LV KHOG
5(6(7 PD\ EH WLHG WR WKH V\VWHP UHVHW FLUFXLWU\ $ V\VWHP UHVHW ZRXOG WKXV DOVR UHVHW WKH )ODVK PHPRU\ HQDEOLQJ WKH V\VWHP WR UHDG WKH ERRWXS ILUPZDUH IURP WKH )ODVK PHPRU\ ,I 5(6(7 LV DVVHUWHG GXULQJ D SURJUDP RU HUDVH RSHUDWLRQ WKH GHYLFH UHTXLUHV D WLPH RI W5($'< GXULQJ (PEHGGHG $OJRULWKPV EHIRUH WKH GHYLFH LV UHDG\ WR UHDG GDWD DJDLQ ,I 5(6(7 LV DVVHUWHG ZKHQ D SURJUDP RU HUDVH RSHUDWLRQ LV QRW H[ HFXWLQJ WKH UHVHW RSHUDWLRQ LV FRPSOHWHG ZLWKLQ D WLPH RI W5($'< QRW GXULQJ (PEHGGHG $OJRULWKPV 7KH V\VWHP FDQ UHDG GDWD W5+ DIWHU 5(6(7 UHWXUQV WR 9,+ 5HIHU WR WKH $& &KDUDFWHULVWLFV VHFWLRQ RQ SDJH IRU 5(6(7 SDUDPHWHUV DQG WR )LJXUH 5HVHW 7LPLQJV RQ SDJH IRU WKH WLPLQJ GLDJUDP
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
39
Preliminary 2XWSXW 'LVDEOH 0RGH
:KHQ WKH 2( LQSXW LV DW 9,+ RXWSXW IURP WKH GHYLFH LV GLVDEOHG 7KH RXWSXWV DUH SODFHG LQ WKH KLJK LPSHGDQFH VWDWH
67$57
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5(6(7
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$OO SUHYLRXVO\ SURWHFWHG VHFWRUV DUH SURWHFWHG RQFH DJDLQ
Figure 1. Temporary Sector Unprotect Operation
40
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A7:A0 = 00000010 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7:A0 = 01000010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 1.5 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0
No No PLSCNT = 25? Yes Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Data = 00h? Yes
Device failed Write reset command
Last sector verified? Yes
No
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove VID from RESET#
Write reset command Sector Unprotect complete
Figure 2.
In-System Sector Protection/Sector Unprotection Algorithms
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
41
Preliminary
Secured Silicon Sector Flash Memory Region
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Table 7.
6HFWRU &XVWRPHU )DFWRU\
Secured Silicon Sector Addresses
6HFWRU 6L]H ZRUGV ZRUGV $GGUHVV 5DQJH K)K K)K
42
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
&XVWRPHUV PD\ RSW WR KDYH WKHLU FRGH SURJUDPPHG E\ )$6/ WKURXJK WKH 6SDQ VLRQ SURJUDPPLQJ VHUYLFH )$6/ SURJUDPV WKH FXVWRPHUV FRGH ZLWK RU ZLWKRXW WKH UDQGRP (61 7KH GHYLFHV DUH WKHQ VKLSSHG IURP )$6/V IDFWRU\ ZLWK WKH )DF WRU\ 6HFXUHG 6LOLFRQ 6HFWRU DQG &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU SHUPDQHQWO\ ORFNHG &RQWDFW WKH ORFDO VDOHV RIILFH IRU GHWDLOV RQ XVLQJ 6SDQVLRQ SURJUDPPLQJ VHUYLFHV &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU 7KH FXVWRPHU ORFNDEOH DUHD LV VKLSSHG XQSURWHFWHG ZKLFK DOORZV WKH FXVWRPHU WR SURJUDP DQG RSWLRQDOO\ ORFN WKH DUHD DV DSSURSULDWH IRU WKH DSSOLFDWLRQ VHFX ULW\ IHDWXUH LV QRW UHTXLUHG WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU FDQ EH WUHDWHG DV DQ DGGLWLRQDO )ODVK PHPRU\ VSDFH 7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU FDQ EH UHDG DQ\ QXPEHU RI WLPHV EXW FDQ EH SURJUDPPHG DQG ORFNHG RQO\ RQFH 1RWH WKDW WKH DFFHOHUDWHG SURJUDPPLQJ $&& DQG XQORFN E\SDVV IXQFWLRQV DUH QRW DYDLODEOH ZKHQ SURJUDPPLQJ WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU EXW UHDG LQJ LQ %DQNV $ % DQG & LV DYDLODEOH 7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU LV ORFDWHG DW DGGUHVVHV K)K 7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU DUHD FDQ EH SURWHFWHG XVLQJ RQH RI WKH IROORZLQJ SURFHGXUHV :ULWH WKH WKUHHF\FOH (QWHU 6HFXUHG 6LOLFRQ 6HFWRU 5HJLRQ FRPPDQG VH TXHQFH DQG WKHQ IROORZ WKH LQV\VWHP VHFWRU SURWHFW DOJRULWKP DV VKRZQ LQ )LJXUH ,Q6\VWHP 6HFWRU 3URWHFWLRQ6HFWRU 8QSURWHFWLRQ $OJRULWKPV RQ SDJH H[FHSW WKDW 5(6(7 PD\ EH DW HLWKHU 9,+ RU 9,' 7KLV DOORZV LQV\V WHP SURWHFWLRQ RI WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU 5HJLRQ ZLWKRXW UDLVLQJ DQ\ GHYLFH SLQ WR D KLJK YROWDJH 1RWH WKDW WKLV PHWKRG LV RQO\ DSSOLFDEOH WR WKH 6HFXUHG 6LOLFRQ 6HFWRU :ULWH WKH 6HFXUHG 6LOLFRQ 6HFWRU 3URWHFWLRQ %LW /RFN FRPPDQG VHTXHQFH 2QFH WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU LV ORFNHG DQG YHULILHG WKH V\VWHP PXVW ZULWH WKH ([LW 6HFXUHG 6LOLFRQ 6HFWRU 5HJLRQ FRPPDQG VHTXHQFH WR UHWXUQ WR UHDGLQJ DQG ZULWLQJ WKH UHPDLQGHU RI WKH DUUD\ 7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU ORFN PXVW EH XVHG ZLWK FDXWLRQ VLQFH RQFH ORFNHG WKHUH LV QR SURFHGXUH DYDLODEOH IRU XQORFNLQJ WKH &XVWRPHU 6HFXUHG 6LOL FRQ 6HFWRU DUHD DQG QRQH RI WKH ELWV LQ WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU PHPRU\ VSDFH FDQ EH PRGLILHG LQ DQ\ ZD\
6HFXUHG 6LOLFRQ 6HFWRU 3URWHFWLRQ %LW
7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU 3URWHFWLRQ %LW SUHYHQWV SURJUDPPLQJ RI WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU PHPRU\ DUHD 2QFH VHW WKH &XVWRPHU 6H FXUHG 6LOLFRQ 6HFWRU PHPRU\ DUHD FRQWHQWV DUH QRQPRGLILDEOH
+DUGZDUH 'DWD 3URWHFWLRQ
7KH FRPPDQG VHTXHQFH UHTXLUHPHQW RI XQORFN F\FOHV IRU SURJUDPPLQJ RU HUDVLQJ SURYLGHV GDWD SURWHFWLRQ DJDLQVW LQDGYHUWHQW ZULWHV UHIHU WR 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH IRU FRPPDQG GHILQLWLRQV 7KH GHYLFH RIIHUV WZR W\SHV RI GDWD SURWHFWLRQ DW WKH VHFWRU OHYHO 7KH 33% DQG '3% DVVRFLDWHG FRPPDQG VHTXHQFHV GLVDEOHV RU UHHQDEOHV ERWK SURJUDP DQG HUDVH RSHUDWLRQV LQ DQ\ VHFWRU RU VHFWRU JURXS :KHQ :3 LV DW 9,/ WKH IRXU RXWHUPRVW VHFWRUV DUH ORFNHG :KHQ $&& LV DW 9,/ DOO VHFWRUV DUH ORFNHG
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
43
Preliminary
7KH IROORZLQJ KDUGZDUH GDWD SURWHFWLRQ PHDVXUHV SUHYHQW DFFLGHQWDO HUDVXUH RU SURJUDPPLQJ ZKLFK PLJKW RWKHUZLVH EH FDXVHG E\ VSXULRXV V\VWHP OHYHO VLJQDOV GXULQJ 9&& SRZHUXS DQG SRZHUGRZQ WUDQVLWLRQV RU IURP V\VWHP QRLVH
Write Protect (WP#)
7KH :ULWH 3URWHFW IHDWXUH SURYLGHV D KDUGZDUH PHWKRG RI SURWHFWLQJ WKH IRXU RXWHUPRVW VHFWRUV 7KLV IXQFWLRQ LV SURYLGHG E\ WKH :3 SLQ DQG RYHUULGHV WKH SUHYLRXVO\ GLVFXVVHG 6HFWRU 3URWHFWLRQ8QSURWHFWLRQ PHWKRG ,I WKH V\VWHP DVVHUWV 9,/ RQ WKH :3 SLQ WKH GHYLFH GLVDEOHV SURJUDP DQG HUDVH IXQFWLRQV LQ WKH IRXU RXWHUPRVW .ZRUG ERRW VHFWRUV 7KH IRXU RXWHUPRVW .ZRUG ERRW VHFWRUV DUH WKH IRXU VHFWRUV FRQWDLQLQJ WKH ORZHVW DGGUHVVHV 6$ 6$ RU WKH IRXU VHFWRUV FRQWDLQLQJ WKH KLJKHVW DGGUHVVHV :6- 6$ 6$ :6- 6$ 6$ RU ERWK WKH ORZHU IRXU 6$ 6$ DQG XSSHU IRXU VHFWRUV :6- 6$ 6$ :6- 6$ 6$ LQ D GXDOERRW FRQILJXUHG GHYLFH ,I WKH V\VWHP DVVHUWV 9,+ RQ WKH :3 SLQ WKH GHYLFH UHYHUWV WR ZKHWKHU WKH XSSHU DQGRU ORZHU IRXU VHFWRUV ZHUH ODVW VHW WR EH SURWHFWHG RU XQSURWHFWHG 7KDW LV VHFWRU SURWHFWLRQ RU XQSURWHFWLRQ IRU WKHVH VHFWRUV GHSHQGV RQ ZKHWKHU WKH\ ZHUH ODVW SURWHFWHG RU XQSURWHFWHG XVLQJ WKH PHWKRG GHVFULEHG LQ 33% 3UR JUDP &RPPDQG VHFWLRQ RQ SDJH 1RWH WKDW WKH :3 SLQ PXVW QRW EH OHIW IORDWLQJ RU XQFRQQHFWHG LQFRQVLVWHQW EH KDYLRU RI WKH GHYLFH PD\ UHVXOW
/RZ 9&& :ULWH ,QKLELW
:KHQ 9&& LV OHVV WKDQ 9/.2 WKH GHYLFH GRHV QRW DFFHSW DQ\ ZULWH F\FOHV 7KLV SUR WHFWV GDWD GXULQJ 9&& SRZHUXS DQG SRZHUGRZQ 7KH FRPPDQG UHJLVWHU DQG DOO LQWHUQDO SURJUDPHUDVH FLUFXLWV DUH GLVDEOHG DQG WKH GHYLFH UHVHWV WR UHDGLQJ DUUD\ GDWD 6XEVHTXHQW ZULWHV DUH LJQRUHG XQWLO 9&& LV JUHDWHU WKDQ 9/.2 7KH V\V WHP PXVW SURYLGH WKH SURSHU VLJQDOV WR WKH FRQWURO LQSXWV WR SUHYHQW XQLQWHQWLRQDO ZULWHV ZKHQ 9&& LV JUHDWHU WKDQ 9/.2
:ULWH 3XOVH *OLWFK 3URWHFWLRQ
1RLVH SXOVHV RI OHVV WKDQ QV W\SLFDO RQ 2( &( F\FOH RU :( GR QRW LQLWLDWH D ZULWH
/RJLFDO ,QKLELW
:ULWH F\FOHV DUH LQKLELWHG E\ KROGLQJ DQ\ RQH RI 2( 9,/ &( 9,+ RU :( 9,+ 7R LQLWLDWH D ZULWH F\FOH &( DQG :( PXVW EH D ORJLFDO ]HUR ZKLOH 2( LV D ORJLFDO RQH
3RZHU8S :ULWH ,QKLELW
,I :( &( 5(6(7 9,/ DQG 2( 9,+ GXULQJ SRZHU XS WKH GHYLFH GRHV QRW DFFHSW FRPPDQGV RQ WKH ULVLQJ HGJH RI :( 7KH LQWHUQDO VWDWH PDFKLQH LV DXWRPDWLFDOO\ UHVHW WR WKH UHDG PRGH RQ SRZHUXS
44
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Common Flash Memory Interface (CFI)
7KH &RPPRQ )ODVK ,QWHUIDFH &), VSHFLILFDWLRQ RXWOLQHV GHYLFH DQG KRVW V\VWHP VRIWZDUH LQWHUURJDWLRQ KDQGVKDNH ZKLFK DOORZV VSHFLILF YHQGRUVSHFLILHG VRIW ZDUH DOJRULWKPV WR EH XVHG IRU HQWLUH IDPLOLHV RI GHYLFHV 6RIWZDUH VXSSRUW FDQ WKHQ EH GHYLFHLQGHSHQGHQW -('(& ,'LQGHSHQGHQW DQG IRUZDUG DQG EDFN ZDUGFRPSDWLEOH IRU WKH VSHFLILHG IODVK GHYLFH IDPLOLHV )ODVK YHQGRUV FDQ VWDQGDUGL]H WKHLU H[LVWLQJ LQWHUIDFHV IRU ORQJWHUP FRPSDWLELOLW\ 7KLV GHYLFH HQWHUV WKH &), 4XHU\ PRGH ZKHQ WKH V\VWHP ZULWHV WKH &), 4XHU\ FRPPDQG K WR DGGUHVV K DQ\ WLPH WKH GHYLFH LV UHDG\ WR UHDG DUUD\ GDWD 7KH V\VWHP FDQ UHDG &), LQIRUPDWLRQ DW WKH DGGUHVVHV JLYHQ LQ 7DEOHV 7R WHUPLQDWH UHDGLQJ &), GDWD WKH V\VWHP PXVW ZULWH WKH UHVHW FRPPDQG 7KH V\VWHP FDQ DOVR ZULWH WKH &), TXHU\ FRPPDQG ZKHQ WKH GHYLFH LV LQ WKH DX WRVHOHFW PRGH 7KH GHYLFH HQWHUV WKH &), TXHU\ PRGH DQG WKH V\VWHP FDQ UHDG &), GDWD DW WKH DGGUHVVHV JLYHQ LQ 7DEOHV 7KH V\VWHP PXVW ZULWH WKH UHVHW FRPPDQG WR UHWXUQ WKH GHYLFH WR WKH DXWRVHOHFW PRGH )RU IXUWKHU LQIRUPDWLRQ SOHDVH UHIHU WR WKH &), 6SHFLILFDWLRQ DQG &), 3XEOLFDWLRQ DYDLODEOH YLD WKH )$6/ VLWH DW WKH IROORZLQJ 85/ K W W S Z Z Z D P G F R P X V H Q ) O D V K 0 H P R U \ 7H F K Q L F D O 5H V R X U F H V BBBAKWPO $OWHUQDWLYHO\ FRQWDFW DQ )$6/ UHSUHVHQ WDWLYH IRU FRSLHV RI WKHVH GRFXPHQWV
Table 8. CFI Query Identification String
$GGUHVVHV K K K K K K K K K K $K 'DWD K K K K K K K K K K K 4XHU\ 8QLTXH $6&,, VWULQJ 45< 'HVFULSWLRQ
3ULPDU\ 2(0 &RPPDQG 6HW $GGUHVV IRU 3ULPDU\ ([WHQGHG 7DEOH $OWHUQDWH 2(0 &RPPDQG 6HW K QRQH H[LVWV QRQH H[LVWV
$GGUHVV IRU $OWHUQDWH 2(0 ([WHQGHG 7DEOH K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
45
Preliminary
Table 9. System Interface String
$GGUHVVHV %K &K 'K (K )K K K K K K K K 'DWD K K K K K K K K K K K K 'HVFULSWLRQ 9&& 0LQ ZULWHHUDVH '' YROW '' PLOOLYROW 9&& 0D[ ZULWHHUDVH '' YROW '' PLOOLYROW 933 0LQ YROWDJH K 933 0D[ YROWDJH K QR 933 SLQ SUHVHQW QR 933 SLQ SUHVHQW
7\SLFDO WLPHRXW SHU VLQJOH E\WHZRUG ZULWH I V 7\SLFDO WLPHRXW IRU 0LQ VL]H EXIIHU ZULWH I V K 7\SLFDO WLPHRXW SHU LQGLYLGXDO EORFN HUDVH PV 7\SLFDO WLPHRXW IRU IXOO FKLS HUDVH I PV K
IA I
QRW VXSSRUWHG
QRW VXSSRUWHG
0D[ WLPHRXW IRU E\WHZRUG ZULWH WLPHV W\SLFDO 0D[ WLPHRXW IRU EXIIHU ZULWH IAWLPHV W\SLFDO 0D[ WLPHRXW SHU LQGLYLGXDO EORFN HUDVH I WLPHV W\SLFDO 0D[ WLPHRXW IRU IXOO FKLS HUDVH I WLPHV W\SLFDO K QRW VXSSRUWHG
Table 10. Device Geometry Definition
$GGUHVVHV K K K $K %K &K 'K (K )K K K K K K K K K K K $K %K &K 'DWD K :6- K :6- K K K K K K K K K )'K :6- 'K :6- K K K K K K K K K K K (UDVH %ORFN 5HJLRQ ,QIRUPDWLRQ 'HYLFH 6L]H I E\WH 'HVFULSWLRQ
)ODVK 'HYLFH ,QWHUIDFH GHVFULSWLRQ UHIHU WR &), SXEOLFDWLRQ 0D[ QXPEHU RI E\WHV LQ PXOWLE\WH ZULWH K QRW VXSSRUWHG I
1XPEHU RI (UDVH %ORFN 5HJLRQV ZLWKLQ GHYLFH (UDVH %ORFN 5HJLRQ ,QIRUPDWLRQ UHIHU WR WKH &), VSHFLILFDWLRQ RU &), SXEOLFDWLRQ
(UDVH %ORFN 5HJLRQ ,QIRUPDWLRQ
(UDVH %ORFN 5HJLRQ ,QIRUPDWLRQ
46
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 11.
$GGUHVVHV K K K K K K 'DWD K K K K K &K
Primary Vendor-Specific Extended Query
'HVFULSWLRQ 4XHU\XQLTXH $6&,, VWULQJ 35, 0DMRU YHUVLRQ QXPEHU $6&,, 0LQRU YHUVLRQ QXPEHU $6&,, $GGUHVV 6HQVLWLYH 8QORFN %LWV 5HTXLUHG 1RW 5HTXLUHG 6LOLFRQ 7HFKQRORJ\ %LWV P 7R 5HDG :ULWH (UDVH 6XVSHQG 1RW 6XSSRUWHG 6HFWRU 3URWHFW 1RW 6XSSRUWHG ;
K K K K $K %K &K 'K (K )K K K K K $K %K
K K K K (K :6- K :6- K K %K &K K K K K :6- K :6- K :6- K :6- K :6- K :6- K :6- K :6-
7R 5HDG 2QO\
1XPEHU RI VHFWRUV LQ SHU JURXS
6HFWRU 7HPSRUDU\ 8QSURWHFW 1RW 6XSSRUWHG 6XSSRUWHG 6HFWRU 3URWHFW8QSURWHFW VFKHPH $GYDQFHG 6HFWRU 3URWHFWLRQ 6LPXOWDQHRXV 2SHUDWLRQ 1XPEHU RI 6HFWRUV LQ DOO EDQNV H[FHSW ERRW EORFN %XUVW 0RGH 7\SH 1RW 6XSSRUWHG 3DJH 0RGH 7\SH 1RW 6XSSRUWHG K K K 6XSSRUWHG :RUG 3DJH :RUG 3DJH :RUG 3DJH
$&& $FFHOHUDWLRQ 6XSSO\ 0LQLPXP 1RW 6XSSRUWHG '' 9ROW '' P9 1RW 6XSSRUWHG '' 9ROW '' P9 'XDO %RRW 'HYLFH K %RWWRP %RRW 'HYLFH K 7RS %RRW 'HYLFH $&& $FFHOHUDWLRQ 6XSSO\ 0D[LPXP 7RS%RWWRP %RRW 6HFWRU )ODJ 3URJUDP 6XVSHQG K %DQN 2UJDQL]DWLRQ ; QRW VXSSRUWHG 1XPEHU RI EDQNV 1XPEHU RI VHFWRUV LQ EDQN 1XPEHU RI VHFWRUV LQ EDQN 1XPEHU RI VHFWRUV LQ EDQN 1XPEHU RI VHFWRUV LQ EDQN
%DQN $ 5HJLRQ ,QIRUPDWLRQ ; %DQN % 5HJLRQ ,QIRUPDWLRQ ; %DQN & 5HJLRQ ,QIRUPDWLRQ ; %DQN ' 5HJLRQ ,QIRUPDWLRQ ;
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
47
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN ' 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K)))K K)))K K)))K K)))K K)))K K)))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
48
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN & 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
49
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN & 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
50
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN & 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
51
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN % 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
52
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN % 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
53
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN % 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
54
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 12.
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN $ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$
WS128J Sector Address Table
6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K))))K )K))))K )$K)$)))K )%K)%)))K )&K)&)))K )'K)')))K )(K)()))K ))K)))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
55
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN ' 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K)))K K)))K K)))K K)))K K)))K K)))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K
56
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN & 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
57
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN & 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K
58
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN % 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
59
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN % 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K)))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K K)))K K))))K
60
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 13. WS064J Sector Address Table
%DQN 6HFWRU 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ %DQN $ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6HFWRU 6L]H .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV .ZRUGV [ $GGUHVV 5DQJH K)))K K))))K K)))K K))))K $K$)))K $K$))))K %K%)))K %K%))))K &K&)))K &K&))))K 'K')))K 'K'))))K (K()))K (K())))K )K))))K )K))))K )K))))K )$K)$)))K )%K)%)))K )&K)&)))K )'K)')))K )(K)()))K ))K)))))K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
61
Preliminary
Command Definitions
:ULWLQJ VSHFLILF DGGUHVV DQG GDWD FRPPDQGV RU VHTXHQFHV LQWR WKH FRPPDQG UHJLVWHU LQLWLDWHV GHYLFH RSHUDWLRQV 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH GHILQHV WKH YDOLG UHJLVWHU FRPPDQG VHTXHQFHV :ULWLQJ LQFRUUHFW DGGUHVV DQG GDWD YDOXHV RU ZULWLQJ WKHP LQ WKH LPSURSHU VHTXHQFH PD\ SODFH WKH GHYLFH LQ DQ XQNQRZQ VWDWH 7KH V\VWHP PXVW ZULWH WKH UHVHW FRPPDQG WR UHWXUQ WKH GHYLFH WR UHDGLQJ DUUD\ GDWD 5HIHU WR WKH $& &KDUDFWHULVWLFV VHFWLRQ IRU WLPLQJ GLDJUDPV
Reading Array Data
7KH GHYLFH LV DXWRPDWLFDOO\ VHW WR UHDGLQJ DUUD\ GDWD DIWHU GHYLFH SRZHUXS 1R FRPPDQGV DUH UHTXLUHG WR UHWULHYH GDWD LQ DV\QFKURQRXV PRGH (DFK EDQN LV UHDG\ WR UHDG DUUD\ GDWD DIWHU FRPSOHWLQJ DQ (PEHGGHG 3URJUDP RU (PEHGGHG (UDVH DOJRULWKP $IWHU WKH GHYLFH DFFHSWV DQ (UDVH 6XVSHQG FRPPDQG WKH FRUUHVSRQGLQJ EDQN HQWHUV WKH HUDVHVXVSHQGUHDG PRGH DIWHU ZKLFK WKH V\VWHP FDQ UHDG GDWD IURP DQ\ QRQHUDVHVXVSHQGHG VHFWRU ZLWKLQ WKH VDPH EDQN $IWHU FRPSOHWLQJ D SUR JUDPPLQJ RSHUDWLRQ LQ WKH (UDVH 6XVSHQG PRGH WKH V\VWHP PD\ RQFH DJDLQ UHDG DUUD\ GDWD IURP DQ\ QRQHUDVHVXVSHQGHG VHFWRU ZLWKLQ WKH VDPH EDQN 6HH WKH (UDVH 6XVSHQG(UDVH 5HVXPH &RPPDQGV VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ 7KH V\VWHP PXVW LVVXH WKH UHVHW FRPPDQG WR UHWXUQ D EDQN WR WKH UHDG RU HUDVH VXVSHQGUHDG PRGH LI '4 JRHV KLJK GXULQJ DQ DFWLYH SURJUDP RU HUDVH RSHUD WLRQ RU LI WKH EDQN LV LQ WKH DXWRVHOHFW PRGH 6HH WKH 5HVHW &RPPDQG VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ 6HH DOVR 5HTXLUHPHQWV IRU $V\QFKURQRXV 5HDG 2SHUDWLRQ 1RQ%XUVW VHFWLRQ RQ SDJH DQG 5HTXLUHPHQWV IRU 6\QFKURQRXV %XUVW 5HDG 2SHUDWLRQ VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ 7KH $V\QFKURQRXV 5HDG DQG 6\QFKURQRXV %XUVW 5HDG WDEOHV SURYLGH WKH UHDG SDUDPHWHUV DQG )LJXUH &/. 6\QFKURQRXV %XUVW 0RGH 5HDG ULVLQJ DFWLYH &/. RQ SDJH )LJXUH 6\QFKURQRXV %XUVW 0RGH 5HDG RQ SDJH DQG )LJXUH $V\QFKURQRXV 0RGH 5HDG ZLWK /DWFKHG $GGUHVVHV RQ SDJH VKRZ WKH WLPLQJV
Set Configuration Register Command Sequence
7KH GHYLFH XVHV D FRQILJXUDWLRQ UHJLVWHU WR VHW WKH YDULRXV EXUVW SDUDPHWHUV QXPEHU RI ZDLW VWDWHV EXUVW UHDG PRGH DFWLYH FORFN HGJH 5'< FRQILJXUDWLRQ DQG V\QFKURQRXV PRGH DFWLYH 7KH FRQILJXUDWLRQ UHJLVWHU PXVW EH VHW EHIRUH WKH GHYLFH ZLOO HQWHU EXUVW PRGH 7KH FRQILJXUDWLRQ UHJLVWHU LV ORDGHG ZLWK D WKUHHF\FOH FRPPDQG VHTXHQFH 7KH ILUVW WZR F\FOHV DUH VWDQGDUG XQORFN VHTXHQFHV 2Q WKH WKLUG F\FOH WKH GDWD VKRXOG EH &K DGGUHVV ELWV $$ VKRXOG EH K DQG DGGUHVV ELWV $$ VHW WKH FRGH WR EH ODWFKHG 7KH GHYLFH ZLOO SRZHU XS RU DIWHU D KDUGZDUH UHVHW ZLWK WKH GHIDXOW VHWWLQJ ZKLFK LV LQ DV\QFKURQRXV PRGH 7KH UHJLVWHU PXVW EH VHW EHIRUH WKH GHYLFH FDQ HQWHU V\QFKURQRXV PRGH 7KH FRQILJXUDWLRQ UHJLVWHU FDQ QRW EH FKDQJHG GXULQJ GHYLFH RSHUDWLRQV SURJUDP HUDVH RU VHFWRU ORFN
62
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1)
Synchronous Read Mode Only
Figure 3. Synchronous/Asynchronous State Diagram
5HDG 0RGH 6HWWLQJ
2Q SRZHUXS RU KDUGZDUH UHVHW WKH GHYLFH LV VHW WR EH LQ DV\QFKURQRXV UHDG PRGH 7KLV VHWWLQJ DOORZV WKH V\VWHP WR HQDEOH RU GLVDEOH EXUVW PRGH GXULQJ V\V WHP RSHUDWLRQV $GGUHVV $ GHWHUPLQHV WKLV VHWWLQJ IRU DV\QFKURQRXV PRGH IRU V\QFKURQRXV PRGH
3URJUDPPDEOH :DLW 6WDWH &RQILJXUDWLRQ
7KH SURJUDPPDEOH ZDLW VWDWH IHDWXUH LQIRUPV WKH GHYLFH RI WKH QXPEHU RI FORFN F\FOHV WKDW PXVW HODSVH DIWHU $9' LV GULYHQ DFWLYH EHIRUH GDWD ZLOO EH DYDLODEOH 7KLV YDOXH LV GHWHUPLQHG E\ WKH LQSXW IUHTXHQF\ RI WKH GHYLFH $GGUHVV ELWV $ $ GHWHUPLQH WKH VHWWLQJ VHH 7DEOH 3URJUDPPDEOH :DLW 6WDWH 6HWWLQJV RQ SDJH 7KH ZDLW VWDWH FRPPDQG VHTXHQFH LQVWUXFWV WKH GHYLFH WR VHW D SDUWLFXODU QXPEHU RI FORFN F\FOHV IRU WKH LQLWLDO DFFHVV LQ EXUVW PRGH 7KH QXPEHU RI ZDLW VWDWHV WKDW VKRXOG EH SURJUDPPHG LQWR WKH GHYLFH LV GLUHFWO\ UHODWHG WR WKH FORFN IUHTXHQF\
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
63
Preliminary
Table 14.
$ $
Programmable Wait State Settings
$ 7RWDO ,QLWLDO $FFHVV &\FOHV GHIDXOW 5HVHUYHG 5HVHUYHG
1RWHV 8SRQ SRZHUXS RU KDUGZDUH UHVHW WKH GHIDXOW VHWWLQJ LV VHYHQ ZDLW VWDWHV 5'< ZLOO GHIDXOW WR EHLQJ DFWLYH ZLWK GDWD ZKHQ WKH :DLW 6WDWH 6HWWLQJ LV VHW WR D WRWDO LQLWLDO DFFHVV F\FOH RI
,W LV UHFRPPHQGHG WKDW WKH ZDLW VWDWH FRPPDQG VHTXHQFH EH ZULWWHQ HYHQ LI WKH GHIDXOW ZDLW VWDWH YDOXH LV GHVLUHG WR HQVXUH WKH GHYLFH LV VHW DV H[SHFWHG $ KDUGZDUH UHVHW ZLOO VHW WKH ZDLW VWDWH WR WKH GHIDXOW VHWWLQJ
6WDQGDUG ZDLWVWDWH +DQGVKDNLQJ 2SWLRQ
7KH KRVW V\VWHP PXVW VHW WKH DSSURSULDWH QXPEHU RI ZDLW VWDWHV LQ WKH IODVK GH YLFH GHSHQGLQJ XSRQ WKH FORFN IUHTXHQF\ 7KH KRVW V\VWHP VKRXOG VHW DGGUHVV ELWV $$ WR IRU D FORFN IUHTXHQF\ RI 0+] 7DEOH GHVFULEHV WKH W\SLFDO QXPEHU RI FORFN F\FOHV ZDLW VWDWHV IRU YDULRXV FRQGLWLRQV
Table 15. Wait States for Standard wait-state Handshaking
7\SLFDO 1R RI &ORFN &\FOHV DIWHU $9' %XUVW 0RGH :RUG RU :RUG RU &RQWLQXRXV :RUG &RQGLWLRQV 9,2 9,2 9 9 0+] /RZ
,Q WKH DQG ZRUG EXUVW UHDG PRGHV WKH DGGUHVV SRLQWHU GRHV QRW FURVV ZRUG ERXQGDULHV DGGUHVVHV ZKLFK DUH PXOWLSOHV RI )K
7KH KRVW V\VWHP PXVW VHW WKH DSSURSULDWH QXPEHU RI ZDLW VWDWHV LQ WKH IODVK GH YLFH GHSHQGLQJ XSRQ WKH FORFN IUHTXHQF\ 7KH DXWRVHOHFW IXQFWLRQ DOORZV WKH KRVW V\VWHP WR GHWHUPLQH ZKHWKHU WKH IODVK GHYLFH LV HQDEOHG IRU KDQGVKDNLQJ 6HH WKH $XWRVHOHFW &RPPDQG 6HTXHQFH VHFWLRQ RQ SDJH IRU PRUH LQIRUPDWLRQ
5HDG 0RGH &RQILJXUDWLRQ
7KH GHYLFH VXSSRUWV IRXU GLIIHUHQW UHDG PRGHV FRQWLQXRXV PRGH DQG DQG ZRUG OLQHDU ZUDS DURXQG PRGHV $ FRQWLQXRXV VHTXHQFH EHJLQV DW WKH VWDUWLQJ DGGUHVV DQG DGYDQFHV WKH DGGUHVV SRLQWHU XQWLO WKH EXUVW RSHUDWLRQ LV FRPSOHWH ,I WKH KLJKHVW DGGUHVV LQ WKH GHYLFH LV UHDFKHG GXULQJ WKH FRQWLQXRXV EXUVW UHDG PRGH WKH DGGUHVV SRLQWHU ZUDSV DURXQG WR WKH ORZHVW DGGUHVV
64
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
)RU H[DPSOH DQ HLJKWZRUG OLQHDU UHDG ZLWK ZUDS DURXQG EHJLQV RQ WKH VWDUWLQJ DGGUHVV ZULWWHQ WR WKH GHYLFH DQG WKHQ DGYDQFHV WR WKH QH[W ZRUG ERXQGDU\ 7KH DGGUHVV SRLQWHU WKHQ UHWXUQV WR WKH VW ZRUG DIWHU WKH SUHYLRXV HLJKW ZRUG ERXQGDU\ ZUDSSLQJ WKURXJK WKH VWDUWLQJ ORFDWLRQ 7KH VL[WHHQ DQG WKLUW\WZR OLQ HDU ZUDS DURXQG PRGHV RSHUDWH LQ D IDVKLRQ VLPLODU WR WKH HLJKWZRUG PRGH 7DEOH VKRZV WKH DGGUHVV ELWV DQG VHWWLQJV IRU WKH IRXU UHDG PRGHV
Table 16.
Read Mode Settings
$GGUHVV %LWV
%XUVW 0RGHV &RQWLQXRXV ZRUG OLQHDU ZUDS DURXQG ZRUG OLQHDU ZUDS DURXQG ZRUG OLQHDU ZUDS DURXQG
$
$
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
65
Preliminary
Table 17.
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Configuration Register
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66
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Autoselect Command Sequence
7KH DXWRVHOHFW FRPPDQG VHTXHQFH DOORZV WKH KRVW V\VWHP WR DFFHVV WKH PDQX IDFWXUHU DQG GHYLFH FRGHV DQG GHWHUPLQH ZKHWKHU RU QRW D VHFWRU LV SURWHFWHG 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH VKRZV WKH DGGUHVV DQG GDWD UH TXLUHPHQWV 7KH DXWRVHOHFW FRPPDQG VHTXHQFH PD\ EH ZULWWHQ WR DQ DGGUHVV ZLWKLQ D EDQN WKDW LV HLWKHU LQ WKH UHDG RU HUDVHVXVSHQGUHDG PRGH 7KH DXWRVH OHFW FRPPDQG PD\ QRW EH ZULWWHQ ZKLOH WKH GHYLFH LV DFWLYHO\ SURJUDPPLQJ RU HUDVLQJ LQ WKH RWKHU EDQN 7KH DXWRVHOHFW FRPPDQG VHTXHQFH LV LQLWLDWHG E\ ILUVW ZULWLQJ WZR XQORFN F\FOHV 7KLV LV IROORZHG E\ D WKLUG ZULWH F\FOH WKDW FRQWDLQV WKH EDQN DGGUHVV DQG WKH DX WRVHOHFW FRPPDQG 7KH EDQN WKHQ HQWHUV WKH DXWRVHOHFW PRGH 1R VXEVHTXHQW GDWD ZLOO EH PDGH DYDLODEOH LI WKH DXWRVHOHFW GDWD LV UHDG LQ V\QFKURQRXV PRGH 7KH V\VWHP PD\ UHDG DW DQ\ DGGUHVV ZLWKLQ WKH VDPH EDQN DQ\ QXPEHU RI WLPHV ZLWKRXW LQLWLDWLQJ DQRWKHU DXWRVHOHFW FRPPDQG VHTXHQFH 5HDG FRPPDQGV WR RWKHU EDQNV ZLOO UHWXUQ GDWD IURP WKH DUUD\ 7KH IROORZLQJ WDEOH GHVFULEHV WKH DG GUHVV UHTXLUHPHQWV IRU WKH YDULRXV DXWRVHOHFW IXQFWLRQV DQG WKH UHVXOWLQJ GDWD %$ UHSUHVHQWV WKH EDQN DGGUHVV DQG 6$ UHSUHVHQWV WKH VHFWRU DGGUHVV 7KH GH YLFH ,' LV UHDG LQ WKUHH F\FOHV 'HVFULSWLRQ 0DQXIDFWXUHU ,' 'HYLFH ,' :RUG 'HYLFH ,' :RUG 'HYLFH ,' :RUG 6HFWRU 3URWHFWLRQ 9HULILFDWLRQ $GGUHVV %$ K %$ K %$ (K %$ )K 6$ K 5HDG 'DWD K (K K :6- (K :6- K :6- K :6- ORFNHG XQORFNHG '4 '4 ,QGLFDWRU %LWV %$ K '4 /RFNHG /RFNHG '4 )DFWRU\ /RFN %LW 1RW /RFNHG 1RW /RFNHG '4 &XVWRPHU /RFN %LW '4 +DQGVKDNH %LW 5HVHUYHG '4 %RRW &RGH 'XDO %RRW 6HFWRU 7RS %RRW 6HFWRU %RWWRP %RRW 6HFWRU '4 '4 6WDQGDUG +DQGVKDNH
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Enter/Exit Secured Silicon Sector Command Sequence
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
67
Preliminary
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Program Command Sequence
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68
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
VHTXHQFHV LQ WKH XQORFN E\SDVV PRGH 7KH HUDVH FRPPDQG VHTXHQFHV DUH IRXU F\FOHV LQ OHQJWK LQVWHDG RI VL[ F\FOHV 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH VKRZV WKH UHTXLUHPHQWV IRU WKH XQORFN E\SDVV FRPPDQG VHTXHQFHV 'XULQJ WKH XQORFN E\SDVV PRGH RQO\ WKH 5HDG 8QORFN %\SDVV 3URJUDP 8QORFN %\SDVV 6HFWRU (UDVH 8QORFN %\SDVV &KLS (UDVH DQG 8QORFN %\SDVV 5HVHW FRP PDQGV DUH YDOLG 7R H[LW WKH XQORFN E\SDVV PRGH WKH V\VWHP PXVW LVVXH WKH WZR F\FOH XQORFN E\SDVV UHVHW FRPPDQG VHTXHQFH 7KH ILUVW F\FOH PXVW FRQWDLQ WKH EDQN DGGUHVV DQG WKH GDWD K 7KH VHFRQG F\FOH QHHG RQO\ FRQWDLQ WKH GDWD K 7KH DUUD\ WKHQ UHWXUQV WR WKH UHDG PRGH 7KH GHYLFH RIIHUV DFFHOHUDWHG SURJUDP RSHUDWLRQV WKURXJK WKH $&& LQSXW :KHQ WKH V\VWHP DVVHUWV 9++ RQ WKLV LQSXW WKH GHYLFH DXWRPDWLFDOO\ HQWHUV WKH 8QORFN %\SDVV PRGH 7KH V\VWHP PD\ WKHQ ZULWH WKH WZRF\FOH 8QORFN %\SDVV SURJUDP FRPPDQG VHTXHQFH 7KH GHYLFH XVHV WKH KLJKHU YROWDJH RQ WKH $&& LQSXW WR DF FHOHUDWH WKH RSHUDWLRQ )LJXUH 3URJUDP 2SHUDWLRQ RQ SDJH LOOXVWUDWHV WKH DOJRULWKP IRU WKH SUR JUDP RSHUDWLRQ 5HIHU WR WKH (UDVH3URJUDP 2SHUDWLRQV WDEOH LQ WKH $& &KDUDFWHULVWLFV VHFWLRQ IRU SDUDPHWHUV DQG )LJXUH $V\QFKURQRXV 3URJUDP 2SHUDWLRQ 7LPLQJV $9' /DWFKHG $GGUHVVHV RQ SDJH DQG )LJXUH 6\Q FKURQRXV 3URJUDP 2SHUDWLRQ 7LPLQJV :( /DWFKHG $GGUHVVHV RQ SDJH IRU WLPLQJ GLDJUDPV
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes Programming Completed
1RWH 6HH 7DEOH IRU SURJUDP FRPPDQG VHTXHQFH
Figure 4.
Program Operation
Chip Erase Command Sequence
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
69
Preliminary
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Sector Erase Command Sequence
6HFWRU HUDVH LV D VL[ EXV F\FOH RSHUDWLRQ 7KH VHFWRU HUDVH FRPPDQG VHTXHQFH LV LQLWLDWHG E\ ZULWLQJ WZR XQORFN F\FOHV IROORZHG E\ D VHWXS FRPPDQG 7ZR DGGL WLRQDO XQORFN F\FOHV DUH ZULWWHQ DQG DUH WKHQ IROORZHG E\ WKH DGGUHVV RI WKH VHFWRU WR EH HUDVHG DQG WKH VHFWRU HUDVH FRPPDQG 7DEOH &RPPDQG 'HIL QLWLRQV RQ SDJH VKRZV WKH DGGUHVV DQG GDWD UHTXLUHPHQWV IRU WKH VHFWRU HUDVH FRPPDQG VHTXHQFH 7KH GHYLFH GRHV QRW UHTXLUH WKH V\VWHP WR SUHSURJUDP SULRU WR HUDVH 7KH (P EHGGHG (UDVH DOJRULWKP DXWRPDWLFDOO\ SURJUDPV DQG YHULILHV WKH HQWLUH PHPRU\ IRU DQ DOO ]HUR GDWD SDWWHUQ SULRU WR HOHFWULFDO HUDVH 7KH V\VWHP LV QRW UHTXLUHG WR SURYLGH DQ\ FRQWUROV RU WLPLQJV GXULQJ WKHVH RSHUDWLRQV $IWHU WKH FRPPDQG VHTXHQFH LV ZULWWHQ D VHFWRU HUDVH WLPHRXW RI QR OHVV WKDQ V RFFXUV 'XULQJ WKH WLPHRXW SHULRG DGGLWLRQDO VHFWRU DGGUHVVHV DQG VHFWRU HUDVH FRPPDQGV PD\ EH ZULWWHQ /RDGLQJ WKH VHFWRU HUDVH EXIIHU PD\ EH GRQH LQ DQ\ VHTXHQFH DQG WKH QXPEHU RI VHFWRUV PD\ EH IURP RQH VHFWRU WR DOO VHFWRUV 7KH WLPH EHWZHHQ WKHVH DGGLWLRQDO F\FOHV PXVW EH OHVV WKDQ V RWKHUZLVH HUD VXUH PD\ EHJLQ $Q\ VHFWRU HUDVH DGGUHVV DQG FRPPDQG IROORZLQJ WKH H[FHHGHG WLPHRXW PD\ RU PD\ QRW EH DFFHSWHG ,W LV UHFRPPHQGHG WKDW SURFHVVRU LQWHU UXSWV EH GLVDEOHG GXULQJ WKLV WLPH WR HQVXUH DOO FRPPDQGV DUH DFFHSWHG 7KH LQWHUUXSWV FDQ EH UHHQDEOHG DIWHU WKH ODVW 6HFWRU (UDVH FRPPDQG LV ZULWWHQ $Q\ FRPPDQG RWKHU WKDQ 6HFWRU (UDVH RU (UDVH 6XVSHQG GXULQJ WKH WLPHRXW SHULRG UHVHWV WKDW EDQN WR WKH UHDG PRGH 7KH V\VWHP PXVW UHZULWH WKH FRPPDQG VH TXHQFH DQG DQ\ DGGLWLRQDO DGGUHVVHV DQG FRPPDQGV 7KH V\VWHP FDQ PRQLWRU '4 WR GHWHUPLQH LI WKH VHFWRU HUDVH WLPHU KDV WLPHG RXW 6HH '4 6HFWRU (UDVH 7LPHU VHFWLRQ RQ SDJH 7KH WLPHRXW EHJLQV IURP WKH ULVLQJ HGJH RI WKH ILQDO :( SXOVH LQ WKH FRPPDQG VHTXHQFH
70
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
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Erase Suspend/Erase Resume Commands
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
71
Preliminary
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Write Erase Command Sequence
Data Poll from System Embedded Erase algorithm in progress No Data = FFh?
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Figure 5. Erase Operation
Password Program Command
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72
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Password Verify Command
7KH 3DVVZRUG 9HULI\ &RPPDQG LV XVHG WR YHULI\ WKH 3DVVZRUG 7KH 3DVVZRUG LV YHULILDEOH RQO\ ZKHQ WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV QRW SURJUDPPHG ,I WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV SURJUDPPHG DQG WKH XVHU DWWHPSWV WR YHULI\ WKH 3DVVZRUG WKH GHYLFH ZLOO DOZD\V GULYH DOO )V RQWR WKH '4 GDWD EXV $OVR WKH GHYLFH ZLOO QRW RSHUDWH LQ 6LPXOWDQHRXV 2SHUDWLRQ ZKHQ WKH 3DVVZRUG 9HULI\ FRPPDQG LV H[HFXWHG 2QO\ WKH SDVVZRUG LV UHWXUQHG UHJDUGOHVV RI WKH EDQN DGGUHVV 7KH ORZHU WZR DGGUHVV ELWV $$ DUH YDOLG GXULQJ WKH 3DVVZRUG 9HULI\ :ULWLQJ WKH 6HFXUHG 6LOLFRQ ([LW FRPPDQG UHWXUQV WKH GHYLFH EDFN WR QRU PDO RSHUDWLRQ
Password Protection Mode Locking Bit Program Command
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Persistent Sector Protection Mode Locking Bit Program Command
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Secured Silicon Sector Protection Bit Program Command
7R SURWHFW WKH 6HFXUHG 6LOLFRQ 6HFWRU ZULWH WKH 6HFXUHG 6LOLFRQ 6HFWRU 3URWHFW FRPPDQG VHTXHQFH ZKLOH LQ WKH 6HFXUHG 6LOLFRQ 6HFWRU PRGH $IWHU LVVXLQJ 23%3K DW WKH IRXUWK EXV F\FOH WKH GHYLFH UHTXLUHV D WLPH RXW SHULRG RI DS SUR[LPDWHO\ V WR SURWHFW WKH 6HFXUHG 6LOLFRQ 6HFWRU 7KHQ E\ ZULWLQJ 23%3 DW WKH ILIWK EXV F\FOH WKH GHYLFH RXWSXWV YHULI\ GDWD DW '4 ,I '4 WKHQ WKH 6HFXUHG 6LOLFRQ 6HFWRU LV SURWHFWHG ,I QRW WKHQ WKH V\VWHP PXVW UHSHDW WKLV SURJUDP VHTXHQFH IURP WKH IRXUWK F\FOH RI 23%3K
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
73
Preliminary
PPB Lock Bit Set Command
7KH 33% /RFN %LW 6HW FRPPDQG LV XVHG WR VHW WKH 33% /RFN ELW LI LW LV FOHDUHG HL WKHU DW UHVHW RU LI WKH 3DVVZRUG 8QORFN FRPPDQG ZDV VXFFHVVIXOO\ H[HFXWHG 7KHUH LV QR 33% /RFN %LW &OHDU FRPPDQG 2QFH WKH 33% /RFN %LW LV VHW LW FDQQRW EH FOHDUHG XQOHVV WKH GHYLFH LV WDNHQ WKURXJK D SRZHURQ FOHDU RU WKH 3DVVZRUG 8QORFN FRPPDQG LV H[HFXWHG 8SRQ VHWWLQJ WKH 33% /RFN %LW WKH 33%V DUH ODWFKHG LQWR WKH '3%V ,I WKH 3DVVZRUG 0RGH /RFNLQJ %LW LV VHW WKH 33% /RFN %LW VWDWXV LV UHIOHFWHG DV VHW HYHQ DIWHU D SRZHURQ UHVHW F\FOH ([LWLQJ WKH 33% /RFN %LW 6HW FRPPDQG LV DFFRPSOLVKHG E\ ZULWLQJ WKH 6HFXUHG 6LOLFRQ ([LW FRPPDQG RQO\ ZKLOH LQ WKH 3HUVLVWHQW 6HFWRU 3URWHFWLRQ 0RGH
DPB Write/Erase/Status Command
7KH '3% :ULWH FRPPDQG LV XVHG WR VHW RU FOHDU D '3% IRU D JLYHQ VHFWRU 7KH KLJK RUGHU DGGUHVV ELWV $PD[$ DUH LVVXHG DW WKH VDPH WLPH DV WKH FRGH K RU K RQ '4'4 $OO RWKHU '4 GDWD EXV SLQV DUH LJQRUHG GXULQJ WKH GDWD ZULWH F\FOH 7KH '3%V DUH PRGLILDEOH DW DQ\ WLPH UHJDUGOHVV RI WKH VWDWH RI WKH 33% RU 33% /RFN %LW ,I WKH 33% LV VHW WKH VHFWRU LV SURWHFWHG UHJDUGOHVV RI WKH YDOXH RI WKH '3% ,I WKH 33% LV FOHDUHG VHWWLQJ WKH '3% WR D SURWHFWV WKH VHFWRU IURP SURJUDPV RU HUDVHV 6LQFH WKLV LV D YRODWLOH ELW UHPRYLQJ SRZHU RU UHVHWWLQJ WKH GHYLFH ZLOO FOHDU WKH '3%V 7KH SURJUDPPLQJ RI WKH '3% IRU D JLYHQ VHFWRU FDQ EH YHULILHG E\ ZULWLQJ D '3% 6WDWXV FRPPDQG WR WKH GHYLFH ([LWLQJ WKH '3% :ULWH(UDVH FRPPDQG LV DFFRPSOLVKHG E\ ZULWLQJ WKH 5HDG5HVHW FRPPDQG ([ LWLQJ WKH '3% 6WDWXV FRPPDQG LV DFFRPSOLVKHG E\ ZULWLQJ WKH 6HFXUHG 6LOLFRQ 6HFWRU ([LW FRPPDQG
Password Unlock Command
7KH 3DVVZRUG 8QORFN FRPPDQG LV XVHG WR FOHDU WKH 33% /RFN %LW VR WKDW WKH 33%V FDQ EH XQORFNHG IRU PRGLILFDWLRQ WKHUHE\ DOORZLQJ WKH 33%V WR EHFRPH DF FHVVLEOH IRU PRGLILFDWLRQ 7KH H[DFW SDVVZRUG PXVW EH HQWHUHG LQ RUGHU IRU WKH XQORFNLQJ IXQFWLRQ WR RFFXU 7KLV FRPPDQG FDQQRW EH LVVXHG DQ\ IDVWHU WKDQ V DW D WLPH WR SUHYHQW D KDFNHU IURP UXQQLQJ WKURXJK WKH DOO ELW FRPELQDWLRQV LQ DQ DWWHPSW WR FRUUHFWO\ PDWFK D SDVVZRUG ,I WKH FRPPDQG LV LVVXHG EHIRUH WKH V H[HFXWLRQ ZLQGRZ IRU HDFK SRUWLRQ RI WKH XQORFN WKH FRPPDQG ZLOO EH LJQRUHG 7KH 3DVVZRUG 8QORFN IXQFWLRQ LV DFFRPSOLVKHG E\ ZULWLQJ 3DVVZRUG 8QORFN FRP PDQG DQG GDWD WR WKH GHYLFH WR SHUIRUP WKH FOHDULQJ RI WKH 33% /RFN %LW 7KH SDVVZRUG LV ELWV ORQJ VR WKH XVHU PXVW ZULWH WKH 3DVVZRUG 8QORFN FRPPDQG WLPHV $ DQG $ DUH XVHG IRU PDWFKLQJ :ULWLQJ WKH 3DVVZRUG 8QORFN FRP PDQG LV QRW DGGUHVV RUGHU VSHFLILF 7KH ORZHU DGGUHVV $$ WKH QH[W 3DVVZRUG 8QORFN FRPPDQG LV WR $$ WKHQ WR $$ DQG ILQDOO\ WR $$ 2QFH WKH 3DVVZRUG 8QORFN FRPPDQG LV HQWHUHG IRU DOO IRXU ZRUGV WKH 5'< SLQ JRHV /2: LQGLFDWLQJ WKDW WKH GHYLFH LV EXV\ $OVR UHDGLQJ WKH %DQN ' UHVXOWV LQ WKH '4 SLQ WRJJOLQJ LQGLFDWLQJ WKDW WKH 3DVVZRUG 8QORFN IXQFWLRQ LV LQ SURJUHVV 5HDGLQJ WKH RWKHU EDQN UHWXUQV DFWXDO DUUD\ GDWD $SSUR[LPDWHO\ V LV UHTXLUHG IRU HDFK SRUWLRQ RI WKH XQORFN 2QFH WKH ILUVW SRUWLRQ RI WKH SDVVZRUG XQORFN FRPSOHWHV 5'< LV QRW GULYHQ DQG '4 GRHV QRW WRJJOH ZKHQ UHDG WKH 3DVVZRUG 8QORFN FRPPDQG LV LVVXHG DJDLQ RQO\ WKLV WLPH ZLWK WKH QH[W SDUW RI WKH SDVVZRUG )RXU 3DVVZRUG 8QORFN FRPPDQGV DUH UHTXLUHG WR VXFFHVVIXOO\ FOHDU WKH 33% /RFN %LW $V ZLWK WKH ILUVW 3DVVZRUG 8QORFN FRPPDQG WKH 5'< VLJ QDO JRHV /2: DQG UHDGLQJ WKH GHYLFH UHVXOWV LQ WKH '4 SLQ WRJJOLQJ RQ VXFFHVVLYH UHDG RSHUDWLRQV XQWLO FRPSOHWH ,W LV WKH UHVSRQVLELOLW\ RI WKH PLFUR
74
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
SURFHVVRU WR NHHS WUDFN RI WKH QXPEHU RI 3DVVZRUG 8QORFN FRPPDQGV WKH RUGHU DQG ZKHQ WR UHDG WKH 33% /RFN ELW WR FRQILUP VXFFHVVIXO SDVVZRUG XQORFN ,Q RUGHU WR UH ORFN WKH GHYLFH LQWR WKH 3DVVZRUG 0RGH WKH 33% /RFN %LW 6HW FRP PDQG FDQ EH UHLVVXHG
PPB Program Command
7KH 33% 3URJUDP FRPPDQG LV XVHG WR SURJUDP RU VHW D JLYHQ 33% (DFK 33% LV LQGLYLGXDOO\ SURJUDPPHG EXW LV EXON HUDVHG ZLWK WKH RWKHU 33%V 7KH VSHFLILF VHFWRU DGGUHVV $PD[$ DUH ZULWWHQ DW WKH VDPH WLPH DV WKH SURJUDP FRP PDQG K ZLWK $ ,I WKH 33% /RFN %LW LV VHW DQG WKH FRUUHVSRQGLQJ 33% LV VHW IRU WKH VHFWRU WKH 33% 3URJUDP FRPPDQG ZLOO QRW H[HFXWH DQG WKH FRPPDQG ZLOO WLPHRXW ZLWKRXW SURJUDPPLQJ WKH 33% $IWHU SURJUDPPLQJ D 33% WZR DGGLWLRQDO F\FOHV DUH QHHGHG WR GHWHUPLQH ZKHWKHU WKH 33% KDV EHHQ SURJUDPPHG ZLWK PDUJLQ $IWHU WK F\FOH WKH GHYLFH UHTXLUHV DSSUR[LPDWHO\ V WLPH RXW SHULRG IRU SURJUDPPLQJ WKH 33% $QG WKHQ DIWHU WK F\FOH WKH GHYLFH RXWSXWV YHULI\ GDWD DW '4 7KH 33% 3URJUDP FRPPDQG GRHV QRW IROORZ WKH (PEHGGHG 3URJUDP DOJRULWKP :ULWLQJ WKH 6HFXUHG 6LOLFRQ 6HFWRU ([LW FRPPDQG UHWXUQV WKH GHYLFH EDFN WR QRU PDO RSHUDWLRQ
All PPB Erase Command
7KH $OO 33% (UDVH FRPPDQG LV XVHG WR HUDVH DOO 33%V LQ EXON 7KHUH LV QR PHDQV IRU LQGLYLGXDOO\ HUDVLQJ D VSHFLILF 33% 8QOLNH WKH 33% SURJUDP QR VSHFLILF VHFWRU DGGUHVV LV UHTXLUHG +RZHYHU ZKHQ WKH 33% HUDVH FRPPDQG LV ZULWWHQ K DQG $ DOO 6HFWRU 33%V DUH HUDVHG LQ SDUDOOHO ,I WKH 33% /RFN %LW LV VHW WKH $// 33% (UDVH FRPPDQG ZLOO QRW H[HFXWH DQG WKH FRPPDQG ZLOO WLPHRXW ZLWK RXW HUDVLQJ WKH 33%V $IWHU HUDVLQJ WKH 33%V WZR DGGLWLRQDO F\FOHV DUH QHHGHG WR GHWHUPLQH ZKHWKHU WKH 33% KDV EHHQ HUDVHG ZLWK PDUJLQ $IWHU WK F\FOH WKH GHYLFH UHTXLUHV DS SUR[LPDWHO\ PV WLPH RXW SHULRG IRU HUDVLQJ WKH 33% $QG WKHQ DIWHU WK F\FOH WKH GHYLFH RXWSXWV YHULI\ GDWD DW '4 ,W LV WKH UHVSRQVLELOLW\ RI WKH XVHU WR SUHSURJUDP DOO 33%V SULRU WR LVVXLQJ WKH $OO 33% (UDVH FRPPDQG ,I WKH XVHU DWWHPSWV WR HUDVH D FOHDUHG 33% RYHUHUDVXUH PD\ RFFXU PDNLQJ LW GLIILFXOW WR SURJUDP WKH 33% DW D ODWHU WLPH $OVR QRWH WKDW WKH WRWDO QXPEHU RI 33% SURJUDPHUDVH F\FOHV LV OLPLWHG WR F\FOHV &\FOLQJ WKH 33%V EH\RQG F\FOHV LV QRW JXDUDQWHHG :ULWLQJ WKH 6HFXUHG 6LOLFRQ 6HF WRU ([LW FRPPDQG UHWXUQV WKH GHYLFH EDFN WR QRUPDO RSHUDWLRQ
PPB Status Command
7KH SURJUDPPLQJ RI WKH 33% IRU D JLYHQ VHFWRU FDQ EH YHULILHG E\ ZULWLQJ D 33% VWDWXV YHULI\ FRPPDQG WR WKH GHYLFH
PPB Lock Bit Status Command
7KH SURJUDPPLQJ RI WKH 33% /RFN %LW IRU D JLYHQ VHFWRU FDQ EH YHULILHG E\ ZULW LQJ D 33% /RFN %LW VWDWXV YHULI\ FRPPDQG WR WKH GHYLFH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
75
Preliminary
Command Definitions
Table 18.
&RPPDQG 6HTXHQFH 1RWH $V\QFKURQRXV 5HDG 1RWH 5HVHW 1RWH $XWRVHOHFW 1RWH 0DQXIDFWXUHU ,' 'HYLFH ,' 1RWH 6HFWRU /RFN 9HULI\ 1RWH ,QGLFDWRU %LWV &\FOHV )LUVW 5$ ;;; %$ %$ 5' ) $$ $$ $$ $$ $$ $$ $$ % $$ $$ &5 & $$ $$ $$ $$ $$ $$ $$ %$ %$ 6$ %$ $ %$ ; %$ ; 6$ ; %$ ; 3$ ( 1RWH 'DWD $$ $$ $$ $$ 6$ %$; 1RWH ( %$ ;) 1RW H
Command Definitions
%XV &\FOHV 1RWHV 7KLUG )RXUWK 'DWD )LIWK $GGU 6L[WK 6HYHQWK
6HFRQG
$GGU 'DWD $GGU 'DWD
$GGU 'DWD $GGU
'DWD $GGU 'DWD $GGU 'DWD

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8QORFN %\SDVV (QWU\ 8QORFN %\SDVV 3URJUDP 1RWHV 8QORFN %\SDVV 0RGH 8QORFN %\SDVV 6HFWRU (UDVH 1RWHV 8QORFN %\SDVV (UDVH 1RWHV 8QORFN %\SDVV 5HVHW 1RWHV

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76
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
77
Preliminary
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78
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Write Operation Status
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DQ7: Data# Polling
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
79
Preliminary
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
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Figure 6. Data# Polling Algorithm
80
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RDY: Ready
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DQ6: Toggle Bit I
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
81
Preliminary
7RJJOH %LW , RQ '4 UHTXLUHV HLWKHU 2( WR VKRZ WKH FKDQJH LQ VWDWH RU &( WR EH GHDVVHUWHHG DQG UHDVVHUWHG
START
Read Byte (DQ0-DQ7) Address = VA Read Byte (DQ0-DQ7) Address = VA
DQ6 = Toggle?
No
Yes
No
DQ5 = 1?
Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA
DQ6 = Toggle?
No
Yes FAIL PASS
1RWH 7KH V\VWHP VKRXOG UHFKHFN WKH WRJJOH ELW HYHQ LI '4 EHFDXVH WKH WRJJOH ELW PD\ VWRS WRJJOLQJ DV '4 FKDQJHV WR 6HH WKH VXEVHFWLRQV RQ '4 DQG '4 IRU PRUH LQIRUPDWLRQ
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
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82
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
'4 WRJJOHV ZKHQ WKH V\VWHP UHDGV DW DGGUHVVHV ZLWKLQ WKRVH VHFWRUV WKDW KDYH EHHQ VHOHFWHG IRU HUDVXUH %XW '4 FDQQRW GLVWLQJXLVK ZKHWKHU WKH VHFWRU LV DF WLYHO\ HUDVLQJ RU LV HUDVHVXVSHQGHG '4 E\ FRPSDULVRQ LQGLFDWHV ZKHWKHU WKH GHYLFH LV DFWLYHO\ HUDVLQJ RU LV LQ (UDVH 6XVSHQG EXW FDQQRW GLVWLQJXLVK ZKLFK VHFWRUV DUH VHOHFWHG IRU HUDVXUH 7KXV ERWK VWDWXV ELWV DUH UHTXLUHG IRU VHFWRU DQG PRGH LQIRUPDWLRQ 5HIHU WR 7DEOH '4 DQG '4 ,QGLFDWLRQV RQ SDJH WR FRPSDUH RXWSXWV IRU '4 DQG '4 6HH WKH IROORZLQJ IRU DGGLWLRQDO LQIRUPDWLRQ )LJXUH 7RJJOH %LW $OJRULWKP RQ SDJH '4 7RJJOH %LW , RQ SDJH )LJXUH 7RJJOH %LW 7LPLQJV 'XULQJ (PEHGGHG $OJRULWKP RQ SDJH DQG 7DEOH '4 DQG '4 ,QGL FDWLRQV RQ SDJH
Table 19. DQ6 and DQ2 Indications
,I GHYLFH LV SURJUDPPLQJ DQG WKH V\VWHP UHDGV DW DQ\ DGGUHVV DW DQ DGGUHVV ZLWKLQ D VHFWRU VHOHFWHG IRU HUDVXUH DW DQ DGGUHVV ZLWKLQ VHFWRUV QRW VHOHFWHG IRU HUDVXUH DW DQ DGGUHVV ZLWKLQ D VHFWRU VHOHFWHG IRU HUDVXUH DW DQ DGGUHVV ZLWKLQ VHFWRUV QRW VHOHFWHG IRU HUDVXUH DW DQ\ DGGUHVV WKHQ '4 WRJJOHV WRJJOHV WRJJOHV GRHV QRW WRJJOH UHWXUQV DUUD\ GDWD WRJJOHV DQG '4 GRHV QRW WRJJOH DOVR WRJJOHV GRHV QRW WRJJOH WRJJOHV UHWXUQV DUUD\ GDWD 7KH V\VWHP FDQ UHDG IURP DQ\ VHFWRU QRW VHOHFWHG IRU HUDVXUH LV QRW DSSOLFDEOH
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HUDVH VXVSHQGHG
SURJUDPPLQJ LQ HUDVH VXVSHQG
Reading Toggle Bits DQ6/DQ2
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
83
Preliminary
V\VWHP WDVNV ,Q WKLV FDVH WKH V\VWHP PXVW VWDUW DW WKH EHJLQQLQJ RI WKH DOJR ULWKP ZKHQ LW UHWXUQV WR GHWHUPLQH WKH VWDWXV RI WKH RSHUDWLRQ )LJXUH 7RJJOH %LW $OJRULWKP RQ SDJH
DQ5: Exceeded Timing Limits
'4 LQGLFDWHV ZKHWKHU WKH SURJUDP RU HUDVH WLPH KDV H[FHHGHG D VSHFLILHG LQWHU QDO SXOVH FRXQW OLPLW 8QGHU WKHVH FRQGLWLRQV '4 SURGXFHV D LQGLFDWLQJ WKDW WKH SURJUDP RU HUDVH F\FOH ZDV QRW VXFFHVVIXOO\ FRPSOHWHG 7KH GHYLFH PD\ RXWSXW D RQ '4 LI WKH V\VWHP WULHV WR SURJUDP D WR D ORFDWLRQ WKDW ZDV SUHYLRXVO\ SURJUDPPHG WR 2QO\ DQ HUDVH RSHUDWLRQ FDQ FKDQJH D EDFN WR D 8QGHU WKLV FRQGLWLRQ WKH GHYLFH KDOWV WKH RSHUDWLRQ DQG ZKHQ WKH WLPLQJ OLPLW KDV EHHQ H[FHHGHG '4 SURGXFHV D 8QGHU ERWK WKHVH FRQGLWLRQV WKH V\VWHP PXVW ZULWH WKH UHVHW FRPPDQG WR UHWXUQ WR WKH UHDG PRGH RU WR WKH HUDVHVXVSHQGUHDG PRGH LI D EDQN ZDV SUHYLRXVO\ LQ WKH HUDVHVXVSHQGSURJUDP PRGH
DQ3: Sector Erase Timer
$IWHU ZULWLQJ D VHFWRU HUDVH FRPPDQG VHTXHQFH WKH V\VWHP PD\ UHDG '4 WR GH WHUPLQH ZKHWKHU RU QRW HUDVXUH KDV EHJXQ 7KH VHFWRU HUDVH WLPHU GRHV QRW DSSO\ WR WKH FKLS HUDVH FRPPDQG ,I DGGLWLRQDO VHFWRUV DUH VHOHFWHG IRU HUDVXUH WKH HQWLUH WLPHRXW DOVR DSSOLHV DIWHU HDFK DGGLWLRQDO VHFWRU HUDVH FRPPDQG :KHQ WKH WLPHRXW SHULRG LV FRPSOHWH '4 VZLWFKHV IURP D WR D ,I WKH WLPH EHWZHHQ DGGLWLRQDO VHFWRU HUDVH FRPPDQGV IURP WKH V\VWHP FDQ EH DV VXPHG WR EH OHVV WKDQ V WKH V\VWHP QHHG QRW PRQLWRU '4 6HH DOVR 6HFWRU (UDVH &RPPDQG 6HTXHQFH RQ SDJH $IWHU WKH VHFWRU HUDVH FRPPDQG LV ZULWWHQ WKH V\VWHP VKRXOG UHDG WKH VWDWXV RI '4 'DWD 3ROOLQJ RU '4 7RJJOH %LW , WR HQVXUH WKDW WKH GHYLFH KDV DFFHSWHG WKH FRPPDQG VHTXHQFH DQG WKHQ UHDG '4 ,I '4 LV WKH (PEHGGHG (UDVH DOJRULWKP KDV EHJXQ DOO IXUWKHU FRPPDQGV H[FHSW (UDVH 6XVSHQG DUH LJQRUHG XQWLO WKH HUDVH RSHUDWLRQ LV FRPSOHWH ,I '4 LV WKH GHYLFH ZLOO DFFHSW DGGL WLRQDO VHFWRU HUDVH FRPPDQGV 7R HQVXUH WKH FRPPDQG KDV EHHQ DFFHSWHG WKH V\VWHP VRIWZDUH VKRXOG FKHFN WKH VWDWXV RI '4 SULRU WR DQG IROORZLQJ HDFK VXE VHTXHQW VHFWRU HUDVH FRPPDQG ,I '4 LV KLJK RQ WKH VHFRQG VWDWXV FKHFN WKH ODVW FRPPDQG PLJKW QRW KDYH EHHQ DFFHSWHG 7DEOH VKRZV WKH VWDWXV RI '4 UHODWLYH WR WKH RWKHU VWDWXV ELWV
84
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Table 20. Write Operation Status
6WDWXV 6WDQGDUG 0RGH (PEHGGHG 3URJUDP $OJRULWKP (PEHGGHG (UDVH $OJRULWKP (UDVH6XVSHQG 5HDG 1RWH (UDVH 6XVSHQGHG 6HFWRU 1RQ(UDVH 6XVSHQGHG 6HFWRU '4 1RWH '4 'DWD '4 '4 7RJJOH 7RJJOH 1R WRJJOH 1RWH 'DWD 7RJJOH '4 1RWH 'DWD '4 1$ 1$ 'DWD 1$ '4 1RWH 1R WRJJOH 1RWH 7RJJOH 7RJJOH 'DWD 1$ 5'< 1RWH +LJK ,PSHGDQFH +LJK ,PSHGDQFH
(UDVH 6XVSHQG 0RGH
(UDVH6XVSHQG3URJUDP
1RWHV '4 VZLWFKHV WR ZKHQ DQ (PEHGGHG 3URJUDP RU (PEHGGHG (UDVH RSHUDWLRQ KDV H[FHHGHG WKH PD[LPXP WLPLQJ OLPLWV 5HIHU WR WKH VHFWLRQ RQ '4 IRU PRUH LQIRUPDWLRQ '4 DQG '4 UHTXLUH D YDOLG DGGUHVV ZKHQ UHDGLQJ VWDWXV LQIRUPDWLRQ 5HIHU WR WKH DSSURSULDWH VXEVHFWLRQ IRU IXUWKHU GHWDLOV :KHQ UHDGLQJ ZULWH RSHUDWLRQ VWDWXV ELWV WKH V\VWHP PXVW DOZD\V SURYLGH WKH EDQN DGGUHVV ZKHUH WKH (PEHGGHG $OJRULWKP LV LQ SURJUHVV 7KH GHYLFH RXWSXWV DUUD\ GDWD LI WKH V\VWHP DGGUHVVHV D QRQEXV\ EDQN 7KH V\VWHP PD\ UHDG HLWKHU DV\QFKURQRXVO\ RU V\QFKURQRXVO\ EXUVW ZKLOH LQ HUDVH VXVSHQG 7KH 5'< SLQ DFWV D GHGLFDWHG RXWSXW WR LQGLFDWH WKH VWDWXV RI DQ HPEHGGHG HUDVH RU SURJUDP RSHUDWLRQ LV LQ SURJUHVV 7KLV LV DYDLODEOH LQ WKH $V\QFKURQRXV PRGH RQO\ :KHQ WKH GHYLFH LV VHW WR $V\QFKURQRXV PRGH WKHVH VWDWXV IODJV VKRXOG EH UHDG E\ &( WRJJOH
Absolute Maximum Ratings
6WRUDJH 7HPSHUDWXUH 3ODVWLF 3DFNDJHV & WR & $PELHQW 7HPSHUDWXUH ZLWK 3RZHU $SSOLHG & WR & 9ROWDJH ZLWK 5HVSHFW WR *URXQG $OO ,QSXWV DQG ,2V H[FHSW DV QRWHG EHORZ 1RWH 9 WR 9,2 9 9&& 1RWH 9 WR 9 9,2 9 WR 9 $ 5(6(7 $&& 1RWH 9 WR 9 2XWSXW 6KRUW &LUFXLW &XUUHQW 1RWH P$
1RWHV 0LQLPXP '& YROWDJH RQ LQSXW RU ,2V LV 9 'XULQJ YROWDJH WUDQVLWLRQV LQSXWV RU ,2V PD\ XQGHUVKRRW 966 WR 9 IRU SHULRGV RI XS WR QV 6HH )LJXUH 0D[LPXP '& YROWDJH RQ LQSXW RU ,2V LV 9&& 9 'XULQJ YROWDJH WUDQVLWLRQV RXWSXWV PD\ RYHUVKRRW WR 9&& 9 IRU SHULRGV XS WR QV 6HH )LJXUH 1R PRUH WKDQ RQH RXWSXW PD\ EH VKRUWHG WR JURXQG DW D WLPH 'XUDWLRQ RI WKH VKRUW FLUFXLW VKRXOG QRW EH JUHDWHU WKDQ RQH VHFRQG 6WUHVVHV DERYH WKRVH OLVWHG XQGHU $EVROXWH 0D[LPXP 5DWLQJV PD\ FDXVH SHUPDQHQW GDPDJH WR WKH GHYLFH 7KLV LV D VWUHVV UDWLQJ RQO\ IXQFWLRQDO RSHUDWLRQ RI WKH GHYLFH DW WKHVH RU DQ\ RWKHU FRQGLWLRQV DERYH WKRVH LQGLFDWHG LQ WKH RSHUDWLRQDO VHFWLRQV RI WKLV GDWD VKHHW LV QRW LPSOLHG ([SRVXUH RI WKH GHYLFH WR DEVROXWH PD[LPXP UDWLQJ FRQGLWLRQV IRU H[WHQGHG SHULRGV PD\ DIIHFW GHYLFH UHOLDELOLW\
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
85
Preliminary
A
QV 9 9 9 QV
QV
Figure 8.
Maximum Negative Overshoot Waveform
QV 9&& 9 9&& 9 9 QV QV
Figure 9. Maximum Positive Overshoot Waveform
Operating Ranges
&RPPHUFLDO & 'HYLFHV $PELHQW 7HPSHUDWXUH 7$& WR & ,QGXVWULDO , 'HYLFHV $PELHQW 7HPSHUDWXUH 7$ & WR & 6XSSO\ 9ROWDJHV 9&& 6XSSO\ 9ROWDJHV 9 WR 9 9,2 6XSSO\ 9ROWDJHV 9 WR 9 9&& !
Operating ranges define those limits between which the functionality of the device is guaranteed.
9,2 P9
86
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
DC Characteristics
CMOS Compatible
3DUDPHWHU ,/, ,/2 'HVFULSWLRQ ,QSXW /RDG &XUUHQW 2XWSXW /HDNDJH &XUUHQW 9,1 9287 &( :( &( :( 7HVW &RQGLWLRQV 1RWHV 966 WR 9&& 9&& 966 WR 9&& 9&& 9,+ 9,/ 2( 9,+ EXUVW OHQJWK 9,+ 9,/ 2( 9,+ EXUVW OHQJWK 9&&PD[ 9&&PD[ 0+] 0+] 0+] 0+] 0+] 0+] 9,+ 0+] ,&& 9&& $FWLYH $V\QFKURQRXV 5HDG &XUUHQW 1RWH &( :( 9,/ 2( 9,+ 9,+ 0+] 0+] ,&& ,&& ,&& ,&& ,&& ,$&& 9,/ 9,+ 92/ 92+ 9,' 9++ 9/.2 9&& $FWLYH :ULWH &XUUHQW 1RWH 9&& 6WDQGE\ &XUUHQW 1RWH 9&& 5HVHW &XUUHQW 9&& $FWLYH &XUUHQW 5HDG :KLOH :ULWH 9&& 6OHHS &XUUHQW $FFHOHUDWHG 3URJUDP &XUUHQW 1RWH ,QSXW /RZ 9ROWDJH ,QSXW +LJK 9ROWDJH 2XWSXW /RZ 9ROWDJH 2XWSXW +LJK 9ROWDJH 9ROWDJH IRU $XWRVHOHFW DQG 7HPSRUDU\ 6HFWRU 8QSURWHFW 9ROWDJH IRU $FFHOHUDWHG 3URJUDP /RZ 9&& /RFNRXW 9ROWDJH &( &( 5(6(7 &( &( &( 9$&& 9,2 9,2 ,2/ ,2+ 9&& 9,/ 2( 5(6(7 9,+ $&& 9&& 9 9,/ 9,+ 9,+ 9$&& 9&& 9,2 9&&
PLQ PLQ
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,&& DFWLYH ZKLOH (PEHGGHG (UDVH RU (PEHGGHG 3URJUDP LV LQ SURJUHVV 'HYLFH HQWHUV DXWRPDWLF VOHHS PRGH ZKHQ DGGUHVVHV DUH VWDEOH IRU W$&& QV 7\SLFDO VOHHS PRGH FXUUHQW LV HTXDO WR ,&& 7RWDO FXUUHQW GXULQJ DFFHOHUDWHG SURJUDPPLQJ LV WKH VXP RI 9$&& DQG 9&& FXUUHQWV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
87
Preliminary
Test Conditions
'HYLFH 8QGHU 7HVW &/
Figure 10.
Test Setup
Table 21. Test Specifications
7HVW &RQGLWLRQ 2XWSXW /RDG &DSDFLWDQFH &/ LQFOXGLQJ MLJ FDSDFLWDQFH ,QSXW 5LVH DQG )DOO 7LPHV ,QSXW 3XOVH /HYHOV ,QSXW WLPLQJ PHDVXUHPHQW UHIHUHQFH OHYHOV 2XWSXW WLPLQJ PHDVXUHPHQW UHIHUHQFH OHYHOV $OO 6SHHG 2SWLRQV 9,2 9,2 9,2 8QLW S) QV 9 9 9
Key to Switching Waveforms
:DYHIRUP ,QSXWV 6WHDG\ &KDQJLQJ IURP + WR / &KDQJLQJ IURP / WR + 'RQW &DUH $Q\ &KDQJH 3HUPLWWHG 'RHV 1RW $SSO\ &KDQJLQJ 6WDWH 8QNQRZQ &HQWHU /LQH LV +LJK ,PSHGDQFH 6WDWH +LJK = 2XWSXWV
88
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Switching Waveforms
All Inputs and Outputs VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output
Figure 11.
Input Waveforms and Measurement Levels
AC Characteristics
VCC Power-up
3DUDPHWHU W9&6 W9,26 W567+ 1RWHV
9&& !
'HVFULSWLRQ 9&& 6HWXS 7LPH 9,2 6HWXS 7LPH 5(6(7 /RZ +ROG 7LPH
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9,2 P9 DQG 9&& UDPS UDWH LV ! 9 V
9&& UDPS UDWH 9 V D +DUGZDUH 5HVHW ZLOO EH UHTXLUHG
tVCS VCC tVIOS VIO
RESET#
Figure 12.
VCC Power-up Diagram
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
89
Preliminary
CLK Characterization
3DUDPHWHU I&/. W&/. W&.+ W&./ W&5 W&) 'HVFULSWLRQ &/. )UHTXHQF\ &/. 3HULRG &/. +LJK 7LPH &/. /RZ 7LPH &/. 5LVH 7LPH &/. )DOO 7LPH 0D[ 0LQ 0LQ 0+] 0+] 8QLW 0+] QV QV
0D[
QV
tCLK tCH tCL
CLK
tCR
tCF
Figure 13. CLK Characterization
90
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Synchronous/Burst Read @ VIO = 1.8 V
3DUDPHWHU -('(& 6WDQGDUG 'HVFULSWLRQ W,$&& W,$&& W%$&& W$&6 W$&+ W%'+ W&5 W2( W&(= W2(= W&(6 W5'<6 W5$&& W$$6 W$$+ W&$6 W$9& W$9' W$&& W&.$ W&.= W2(6 /DWHQF\ 6WDQGDUG ZDLWVWDWH +DQGVKDNH PRGH IRU :RUG DQG :RUG %XUVW /DWHQF\ 6WDQGDUG ZDLWVWDWH +DQGVKDNH PRGH IRU :RUG DQG &RQWLQXRXV %XUVW %XUVW $FFHVV 7LPH 9DOLG &ORFN WR 2XWSXW 'HOD\ $GGUHVV 6HWXS 7LPH WR &/. 6HH 1RWH $GGUHVV +ROG 7LPH IURP &/. 6HH 1RWH 'DWD +ROG 7LPH IURP 1H[W &ORFN &\FOH &KLS (QDEOH WR 5'< 9DOLG 2XWSXW (QDEOH WR 2XWSXW 9DOLG &KLS (QDEOH WR +LJK = 2XWSXW (QDEOH WR +LJK = &( 6HWXS 7LPH WR &/. 0D[ 0D[ 0D[ 0LQ 0LQ 0LQ 0D[ 0D[ 0D[ 0D[ 0LQ 0LQ 0D[ 6HH 1RWH 6HH 1RWH 0LQ 0LQ 0LQ 0LQ 0LQ 0D[ 0D[ 0D[ 0LQ 0+] 0+] 8QLW QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV
5'< 6HWXS 7LPH WR &/. 5HDG\ $FFHVV 7LPH IURP &/. $GGUHVV 6HWXS 7LPH WR $9' $GGUHVV +ROG 7LPH WR $9' &( $9' $9' 6HWXS 7LPH WR $9' /RZ WR &/. 3XOVH
$FFHVV 7LPH &/. WR DFFHVV UHVXPH &/. WR +LJK = 2XWSXW (QDEOH 6HWXS 7LPH
1RWH $GGUHVVHV DUH ODWFKHG RQ WKH ILUVW RI HLWKHU WKH DFWLYH HGJH RI &/. RU WKH ULVLQJ HGJH RI $9'
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
91
Preliminary
AC CHaracteristics
CE# CLK tAVC AVD# tACS Addresses
Aa
tCES 1 2 3
7 cycles for initial access shown.
tCEZ 6 7
4
5
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
Da + n
tOEZ tRACC
Hi-Z
tOE
tRDYS
1RWHV )LJXUH VKRZV WRWDO QXPEHU RI ZDLW VWDWHV VHW WR VHYHQ F\FOHV 7KH WRWDO QXPEHU RI ZDLW VWDWHV FDQ EH SURJUDPPHG IURP WZR F\FOHV WR VHYHQ F\FOHV ,I DQ\ EXUVW DGGUHVV RFFXUV DW D ZRUG ERXQGDU\ WZR DGGLWLRQDO FORFN F\FOH DUH LQVHUWHG DQG LV LQGLFDWHG E\ 5'< 7KH GHYLFH LV LQ V\QFKURQRXV PRGH
Figure 14. CLK Synchronous Burst Mode Read (rising active CLK)
CE# CLK tAVC AVD# tACS Addresses
Aa
tCES 1
4 cycles for initial access shown.
tCEZ 5
2
3
4
tAVD tBDH tBACC
Hi-Z
tACH Data tIACC tACC OE#
Hi-Z Da
Da + 1
Da + n
tOEZ tRACC
Hi-Z
tCR
tOE
RDY tRDYS
1RWHV )LJXUH VKRZV WRWDO QXPEHU RI ZDLW VWDWHV VHW WR IRXU F\FOHV 7KH WRWDO QXPEHU RI ZDLW VWDWHV FDQ EH SURJUDPPHG IURP WZR F\FOHV WR VHYHQ F\FOHV &ORFN LV VHW IRU DFWLYH IDOOLQJ HGJH ,I DQ\ EXUVW DGGUHVV RFFXUV DW D ZRUG ERXQGDU\ WZR DGGLWLRQDO FORFN F\FOH DUH LQVHUWHG DQG LV LQGLFDWHG E\ 5'< 7KH GHYLFH LV LQ V\QFKURQRXV PRGH
Figure 15.
CLK Synchronous Burst Mode Read (Falling Active Clock)
92
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
tCAS CE# 1 CLK tAVC AVD# tAAS Addresses
Aa 7 cycles for initial access shown.
tCEZ 5 6 7
2
3
4
tAVD
tAAH Data tIACC tACC OE# tCR RDY
Hi-Z Da Da + 1
tBACC
Hi-Z Da + n
tBDH tRACC
tOEZ
tOE
Hi-Z
tRDYS
1RWHV )LJXUH VKRZV WRWDO QXPEHU RI ZDLW VWDWHV VHW WR VHYHQ F\FOHV 7KH WRWDO QXPEHU RI ZDLW VWDWHV FDQ EH SURJUDPPHG IURP WZR F\FOHV WR VHYHQ F\FOHV &ORFN LV VHW IRU DFWLYH ULVLQJ HGJH ,I DQ\ EXUVW DGGUHVV RFFXUV DW D ZRUG ERXQGDU\ WZR DGGLWLRQDO FORFN F\FOH DUH LQVHUWHG DQG LV LQGLFDWHG E\ 5'< 7KH GHYLFH LV LQ V\QFKURQRXV PRGH
Figure 16.
Synchronous Burst Mode Read
tCES CE# 1 CLK tAVC AVD# tACS Addresses
AC
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH
tOE
tRACC
tRACC
tRDYS
1RWHV )LJXUH VKRZV WRWDO QXPEHU RI ZDLW VWDWHV VHW WR VHYHQ F\FOHV 7KH WRWDO QXPEHU RI ZDLW VWDWHV FDQ EH SURJUDPPHG IURP WZR F\FOHV WR VHYHQ F\FOHV &ORFN LV VHW IRU DFWLYH ULVLQJ HGJH ,I DQ\ EXUVW DGGUHVV RFFXUV DW D ZRUG ERXQGDU\ WZR DGGLWLRQDO FORFN F\FOH DUH LQVHUWHG DQG LV LQGLFDWHG E\ 5'< 7KH GHYLFH LV LQ V\QFKURQRXV PRGH ZLWK ZUDS DURXQG '' LQ GDWD ZDYHIRUP LQGLFDWHV WKH RUGHU WKH GDWD ZLWKLQ D JLYHQ ZRUG DGGUHVV UDQJH IURP ORZHVW WR KLJKHVW 6WDUWLQJ DGGUHVV LQ ILJXUH LV WKH WK DGGUHVV LQ UDQJH $&
Figure 17. 8-word Linear Burst with Wrap Around
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
93
Preliminary
AC Characteristics
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa 6 wait cycles for initial access shown.
tCEZ 6
2
3
4
5
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z Da Da+1
tBACC
Hi-Z Da+2 Da+3 Da + n
tRACC tOE
tBDH
tOEZ
Hi-Z
tRDYS
1RWHV )LJXUH DVVXPHV ZDLW VWDWHV IRU LQLWLDO DFFHVV DQG V\QFKURQRXV UHDG 7KH 6HW &RQILJXUDWLRQ 5HJLVWHU FRPPDQG VHTXHQFH KDV EHHQ ZULWWHQ ZLWK $ GHYLFH ZLOO RXWSXW 5'< RQH F\FOH EHIRUH YDOLG GDWD
Figure 18.
Linear Burst with RDY Set One Cycle Before Data
94
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Asynchronous Mode Read @ VIO = 1.8 V
3DUDPHWHU -('(& 6WDQGDUG 'HVFULSWLRQ W&( W$&& W$9'3 W$$9'6 W$$9'+ W2( W2(+ W2(= W&$6
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0+] /RZ 0D[ 0D[ 0LQ 0LQ 0LQ 0D[ 0LQ 3ROOLQJ 0LQ 0D[ 0LQ
0+]
8QLW QV QV QV QV QV
$FFHVV 7LPH IURP &(
$V\QFKURQRXV $FFHVV 7LPH 1RWH $9' /RZ 7LPH
$GGUHVV 6HWXS 7LPH WR 5LVLQJ (GJH RI $9' $GGUHVV +ROG 7LPH IURP 5LVLQJ (GJH RI $9' 2XWSXW (QDEOH WR 2XWSXW 9DOLG 2XWSXW (QDEOH +ROG 7LPH 5HDG 7RJJOH DQG 'DWD
QV QV QV QV QV
2XWSXW (QDEOH WR +LJK = 1RWH &( 6HWXS 7LPH WR $9'
$V\QFKURQRXV $FFHVV 7LPH LV IURP WKH ODVW RI HLWKHU VWDEOH DGGUHVVHV RU WKH IDOOLQJ HGJH RI $9' 1RW WHVWHG
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
95
Preliminary
AC Characteristics
CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS RA tAAVDH tCE Valid RD tOEZ
OE#
1RWH 5$
5HDG $GGUHVV 5'
5HDG 'DWD
Figure 19. Asynchronous Mode Read with Latched Addresses
CE# tOE tOEH WE# Data tACC Addresses RA tCE Valid RD tOEZ
OE#
AVD#
1RWH 5$ 5HDG $GGUHVV 5' 5HDG 'DWD
Figure 20. Asynchronous Mode Read
96
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Hardware Reset (RESET#)
3DUDPHWHU -('(& 6WG W5HDG\ W5HDG\ W53 W5+ W53' 1RWH 1RW 'HVFULSWLRQ 5(6(7 3LQ /RZ 'XULQJ (PEHGGHG $OJRULWKPV WR 5HDG 0RGH 6HH 1RWH 5(6(7 3LQ /RZ 127 'XULQJ (PEHGGHG $OJRULWKPV WR 5HDG 0RGH 6HH 1RWH 5(6(7 3XOVH :LGWK 0D[ 0D[ 0LQ 0LQ 0LQ $OO 6SHHG 2SWLRQV 8QLW V QV QV QV V
5HVHW +LJK 7LPH %HIRUH 5HDG 6HH 1RWH 5(6(7 WHVWHG /RZ WR 6WDQGE\ 0RGH
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CE#, OE# tReady RESET# tRP
Figure 21. Reset Timings
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
97
Preliminary
AC Characteristics
Erase/Program Operations @ VIO = 1.8 V
3DUDPHWHU -('(& W$9$9 W$9:/ 6WDQGDUG 'HVFULSWLRQ W:& W$6 :ULWH &\FOH 7LPH 1RWH $GGUHVV 6HWXS 7LPH 1RWHV 6\QFKURQRXV $V\QFKURQRXV $GGUHVV +ROG 7LPH 1RWHV $9' /RZ 7LPH 6\QFKURQRXV $V\QFKURQRXV 0LQ 0LQ 0+] 0+] 8QLW QV QV
W:/$;
W$+ W$9'3
0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 7\S 7\S 7\S 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ 0LQ
QV QV QV QV QV QV QV QV QV QV V V VHF QV V V QV QV QV QV QV
W'9:+ W:+'; W*+:/
W'6 W'+ W*+:/ W&$6
'DWD 6HWXS 7LPH 'DWD +ROG 7LPH 5HDG 5HFRYHU\ 7LPH %HIRUH :ULWH &( &( 6HWXS 7LPH WR $9' +ROG 7LPH
W:+(+ W:/:+ W:+:/
W&+ W:3 W:3+ W65:
:ULWH 3XOVH :LGWK :ULWH 3XOVH :LGWK +LJK /DWHQF\ %HWZHHQ 5HDG DQG :ULWH 2SHUDWLRQV 3URJUDPPLQJ 2SHUDWLRQ 1RWH $FFHOHUDWHG 3URJUDPPLQJ 2SHUDWLRQ 1RWH 6HFWRU (UDVH 2SHUDWLRQ 1RWHV &KLS (UDVH 2SHUDWLRQ 1RWHV 9$&& 5LVH DQG )DOO 7LPH 9$&& 6HWXS 7LPH 'XULQJ $FFHOHUDWHG 3URJUDPPLQJ 9&& 6HWXS 7LPH &( $9' $9' $9' 6HWXS 7LPH WR :( 6HWXS 7LPH WR :( +ROG 7LPH WR :( +ROG 7LPH WR &/.
W:+:+ W:+:+ W:+:+
W:+:+ W:+:+ W:+:+ W9,' W9,'6 W9&6
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W&6 W$96: W$9+: W$9+& W&6:
&ORFN 6HWXS 7LPH WR :(
1RWHV 1RW
WHVWHG
$V\QFKURQRXV PRGH DOORZV ERWK $V\QFKURQRXV DQG 6\QFKURQRXV SURJUDP RSHUDWLRQ 6\QFKURQRXV PRGH DOORZV ERWK $V\QFKURQRXV DQG 6\QFKURQRXV SURJUDP RSHUDWLRQ ,Q DV\QFKURQRXV SURJUDP RSHUDWLRQ WLPLQJ DGGUHVVHV DUH ODWFKHG RQ WKH IDOOLQJ HGJH RI :( RU ULVLQJ HGJH RI $9' ,Q V\QFKURQRXV SURJUDP RSHUDWLRQ WLPLQJ DGGUHVVHV DUH ODWFKHG RQ WKH ILUVW RI HLWKHU WKH ULVLQJ HGJH RI $9' RU WKH DFWLYH HGJH RI &/. 6HH WKH (UDVH DQG 3URJUDPPLQJ 3HUIRUPDQFH VHFWLRQ IRU PRUH LQIRUPDWLRQ 'RHV QRW LQFOXGH WKH SUHSURJUDPPLQJ WLPH
98
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
VIH
Program Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 555h tAH PA VA
In Progress
VA
Data
A0h
PD tDS tDH
Complete
CE#
OE# tWP WE# tCS
tCH
tWHWH1 tWPH tWC
tVCS VCC
1RWHV 3$ 3URJUDP $GGUHVV 3' 3URJUDP 'DWD 9$ 9DOLG $GGUHVV IRU UHDGLQJ VWDWXV ELWV ,Q SURJUHVV DQG FRPSOHWH UHIHU WR VWDWXV RI SURJUDP RSHUDWLRQ $$ DUH GRQW FDUH GXULQJ FRPPDQG VHTXHQFH XQORFN F\FOHV &/. FDQ EH HLWKHU 9,/ RU 9,+ 7KH $V\QFKURQRXV SURJUDPPLQJ RSHUDWLRQ LV LQGHSHQGHQW RI WKH 6HW 'HYLFH 5HDG 0RGH ELW LQ WKH &RQILJXUDWLRQ 5HJ LVWHU
Figure 22. Asynchronous Program Operation Timings: AVD# Latched Addresses
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
99
Preliminary
AC Characteristics
Program Command Sequence (last two cycles) CLK tACS tCSW AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE# tAVSW
A0h
PD tDS tDH
Complete
OE#
tAH tWP
tCH
WE#
tWHWH1 tWPH tWC
tVCS VCC
1RWHV 3$ 3URJUDP $GGUHVV 3' 3URJUDP 'DWD 9$ 9DOLG $GGUHVV IRU UHDGLQJ VWDWXV ELWV ,Q SURJUHVV DQG FRPSOHWH UHIHU WR VWDWXV RI SURJUDP RSHUDWLRQ $$ DUH GRQW FDUH GXULQJ FRPPDQG VHTXHQFH XQORFN F\FOHV &/. FDQ EH HLWKHU 9,/ RU 9,+ 7KH $V\QFKURQRXV SURJUDPPLQJ RSHUDWLRQ LV LQGHSHQGHQW RI WKH 6HW 'HYLFH 5HDG 0RGH ELW LQ WKH &RQILJXUDWLRQ 5HJ LVWHU
Figure 23. Asynchronous Program Operation Timings: WE# Latched Addresses
100
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Program Command Sequence (last two cycles) tAVCH CLK tACS tCSW AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE# tAVSW
A0h
PD tDS tDH
Complete
OE#
tAH tWP
tCH
WE#
tWHWH1 tWPH tWC
tVCS VCC
1RWHV 3$ 3URJUDP $GGUHVV 3' 3URJUDP 'DWD 9$ 9DOLG $GGUHVV IRU UHDGLQJ VWDWXV ELWV ,Q SURJUHVV DQG FRPSOHWH UHIHU WR VWDWXV RI SURJUDP RSHUDWLRQ $$ DUH GRQW FDUH GXULQJ FRPPDQG VHTXHQFH XQORFN F\FOHV $GGUHVVHV DUH ODWFKHG RQ WKH ILUVW RI HLWKHU WKH ULVLQJ HGJH RI $9' RU WKH DFWLYH HGJH RI &/. (LWKHU &( RU $9' LV UHTXLUHG WR JR IURP ORZ WR KLJK LQ EHWZHHQ SURJUDPPLQJ FRPPDQG VHTXHQFHV 7KH 6\QFKURQRXV SURJUDPPLQJ RSHUDWLRQ LV GHSHQGHQW RI WKH 6HW 'HYLFH 5HDG 0RGH ELW LQ WKH &RQILJXUDWLRQ 5HJLVWHU 7KH &RQILJXUDWLRQ 5HJLVWHU PXVW EH VHW WR WKH 6\QFKURQRXV 5HDG 0RGH
Figure 24. Synchronous Program Operation Timings: WE# Latched Addresses
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
101
Preliminary
AC Characteristics
Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD# tAVDP Addresses 555h PA VA
In Progress
Read Status Data
VA
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWPH tWC
tVCS VCC
1RWHV 3$ 3URJUDP $GGUHVV 3' 3URJUDP 'DWD 9$ 9DOLG $GGUHVV IRU UHDGLQJ VWDWXV ELWV ,Q SURJUHVV DQG FRPSOHWH UHIHU WR VWDWXV RI SURJUDP RSHUDWLRQ $$ DUH GRQW FDUH GXULQJ FRPPDQG VHTXHQFH XQORFN F\FOHV $GGUHVVHV DUH ODWFKHG RQ WKH ILUVW RI HLWKHU WKH ULVLQJ HGJH RI $9' RU WKH DFWLYH HGJH RI &/. (LWKHU &( RU $9' LV UHTXLUHG WR JR IURP ORZ WR KLJK LQ EHWZHHQ SURJUDPPLQJ FRPPDQG VHTXHQFHV 7KH 6\QFKURQRXV SURJUDPPLQJ RSHUDWLRQ LV GHSHQGHQW RI WKH 6HW 'HYLFH 5HDG 0RGH ELW LQ WKH &RQILJXUDWLRQ 5HJLVWHU 7KH &RQILJXUDWLRQ 5HJLVWHU PXVW EH VHW WR WKH 6\QFKURQRXV 5HDG 0RGH
Figure 25.
Synchronous Program Operation Timings: CLK Latched Addresses
102
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
VIH
Erase Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
tCH
tWHWH2 tWPH tWC
Figure 26. Chip/Sector Erase Command Sequence
1RWHV 6$ LV WKH VHFWRU DGGUHVV IRU 6HFWRU (UDVH $GGUHVV ELWV $$ DUH GRQW FDUHV GXULQJ XQORFN F\FOHV LQ WKH FRPPDQG VHTXHQFH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
103
Preliminary
AC Characteristics
CE#
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
1 s
tVIDS tVID
VIL or VIH
1RWH 8VH VHWXS DQG KROG WLPHV IURP FRQYHQWLRQDO SURJUDP RSHUDWLRQ
Figure 27.
Accelerated Unlock Bypass Programming Timing
104
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Status Data
Status Data
1RWHV 6WDWXV UHDGV LQ ILJXUH DUH VKRZQ DV DV\QFKURQRXV 9$ 9DOLG $GGUHVV 7ZR UHDG F\FOHV DUH UHTXLUHG WR GHWHUPLQH VWDWXV :KHQ WKH (PEHGGHG $OJRULWKP RSHUDWLRQ LV FRPSOHWH DQG 'DWD 3ROOLQJ ZLOO RXWSXW WUXH GDWD :KLOH LQ $V\QFKURQRXV PRGH 5'< ZLOO EH ORZ ZKLOH WKH GHYLFH LV LQ HPEHGGHG HUDVH RU SURJUDPPLQJ PRGH
Figure 28.
Data# Polling Timings (During Embedded Algorithm)
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ
Data
Status Data
Status Data
1RWHV 6WDWXV UHDGV LQ ILJXUH DUH VKRZQ DV DV\QFKURQRXV 9$ 9DOLG $GGUHVV 7ZR UHDG F\FOHV DUH UHTXLUHG WR GHWHUPLQH VWDWXV :KHQ WKH (PEHGGHG $OJRULWKP RSHUDWLRQ LV FRPSOHWH WKH WRJJOH ELWV ZLOO VWRS WRJJOLQJ :KLOH LQ $V\QFKURQRXV PRGH 5'< ZLOO EH ORZ ZKLOH WKH GHYLFH LV LQ HPEHGGHG HUDVH RU SURJUDPPLQJ PRGH
Figure 29.
Toggle Bit Timings (During Embedded Algorithm)
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
105
Preliminary
AC Characteristics
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
1RWHV 7KH WLPLQJV DUH VLPLODU WR V\QFKURQRXV UHDG WLPLQJV 9$ 9DOLG $GGUHVV 7ZR UHDG F\FOHV DUH UHTXLUHG WR GHWHUPLQH VWDWXV :KHQ WKH (PEHGGHG $OJRULWKP RSHUDWLRQ LV FRPSOHWH WKH WRJJOH ELWV ZLOO VWRS WRJJOLQJ 5'< LV DFWLYH ZLWK GDWD $ LQ WKH &RQILJXUDWLRQ 5HJLVWHU :KHQ $ LQ WKH &RQILJXUDWLRQ 5HJLVWHU 5'< LV DFWLYH RQH FORFN F\FOH EHIRUH GDWD
Figure 30.
Synchronous Data Polling Timings/Toggle Bit Timings
(QWHU (PEHGGHG (UDVLQJ :(
(UDVH 6XVSHQG (UDVH
(QWHU (UDVH 6XVSHQG 3URJUDP
(UDVH 5HVXPH (UDVH (UDVH &RPSOHWH
(UDVH 6XVSHQG 5HDG
(UDVH (UDVH 6XVSHQG 6XVSHQG 5HDG 3URJUDP
'4 '4
1RWH '4 WRJJOHV RQO\ ZKHQ UHDG DW DQ DGGUHVV ZLWKLQ DQ HUDVHVXVSHQGHG VHFWRU 7KH V\VWHP PD\ XVH 2( WR WRJJOH '4 DQG '4 RU &(
Figure 31.
DQ2 vs. DQ6
106
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Temporary Sector Unprotect
3DUDPHWHU -('(& 6WG W9,'5 W9++ W563 W55%
1RWH 1RW
'HVFULSWLRQ 9,' 5LVH DQG )DOO 7LPH 6HH 1RWH 9++ 5LVH DQG )DOO 7LPH 6HH 1RWH 5(6(7 6HWXS 7LPH IRU 7HPSRUDU\ 6HFWRU 8QSURWHFW 5(6(7 +ROG 7LPH IURP 5'< +LJK IRU 7HPSRUDU\ 6HFWRU 8QSURWHFW 0LQ 0LQ 0LQ 0LQ
$OO 6SHHG 2SWLRQV
8QLW QV QV V V
WHVWHG
VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID
VIL or VIH
WE# tRSP RDY tRRB
Figure 32.
Temporary Sector Unprotect Timing Diagram
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
107
Preliminary
AC Characteristics
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid* Verify 40h
Sector Protect: 150 s Sector Unprotect: 1.5 ms
Valid*
Data 1 s CE#
60h
60h
Status
WE#
OE#
)RU VHFWRU SURWHFW $ $ $ )RU VHFWRU XQSURWHFW $ $ $
Figure 33.
Sector/Sector Block Protect and Unprotect Timing Diagram
108
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C64 40
C65 41
C66 42
C67 43
tRACC RDY (Note 1) tRACC RDY (Note 2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
D64
D65
D66
D67
1RWHV 5'< DFWLYH ZLWK GDWD $
LQ WKH &RQILJXUDWLRQ 5HJLVWHU
5'< DFWLYH RQH FORFN F\FOH EHIRUH GDWD $ LQ WKH &RQILJXUDWLRQ 5HJLVWHU &[[ LQGLFDWHV WKH FORFN WKDW WULJJHUV '[[ RQ WKH RXWSXWV IRU H[DPSOH & WULJJHUV ' )LJXUH VKRZV WKH GHYLFH QRW FURVVLQJ D EDQN LQ WKH SURFHVV RI SHUIRUPLQJ DQ HUDVH RU SURJUDP ,I WKH VWDUWLQJ DGGUHVV ODWFKHG LQ LV HLWKHU (K RU )K RU VRPH PXOWLSOH RI HLWKHU WKHUH LV QR DGGLWLRQDO F\FOH ODWHQF\ DW WKH ERXQGDU\ FURVVLQJ
Figure 34.
Latency with Boundary Crossing
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
109
Preliminary
AC Characteristics
Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60 CLK Address (hex) AVD# 3C (stays high)
C61 3D
C62 3E
C63 3F
C63 3F
C63 3F
C64 40
tRACC RDY (Note 1) tRACC RDY (Note 2)
latency latency
tRACC
tRACC
Data
D60
D61
D62
D63
Invalid
Read Status
OE#, CE#
(stays low)
1RWHV 5'< DFWLYH ZLWK GDWD $ LQ WKH &RQILJXUDWLRQ 5HJLVWHU 5'< DFWLYH RQH FORFN F\FOH EHIRUH GDWD $ LQ WKH &RQILJXUDWLRQ 5HJLVWHU &[[ LQGLFDWHV WKH FORFN WKDW WULJJHUV '[[ RQ WKH RXWSXWV IRU H[DPSOH & WULJJHUV ' )LJXUH VKRZV WKH GHYLFH FURVVLQJ D EDQN LQ WKH SURFHVV RI SHUIRUPLQJ DQ HUDVH RU SURJUDP
Figure 35. Latency with Boundary Crossing into Program/Erase Bank
110
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
Data D0 D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following addresses being latched
OE# 1 CLK 0 1 2 3
4
5
6
7
2
3
4
5
number of clock cycles programmed
:DLW 6WDWH 'HFRGLQJ $GGUHVVHV
A14, A13, A12 = "111" Reserved A14, A13, A12 = "110" Reserved A14, A13, A12 = "101" 5 programmed, 7 total A14, A13, A12 = "100" 4 programmed, 6 total A14, A13, A12 = "011" 3 programmed, 5 total A14, A13, A12 = "010" 2 programmed, 4 total A14, A13, A12 = "001" 1 programmed, 3 total A14, A13, A12 = "000" 0 programmed, 2 total
1RWH )LJXUH DVVXPHV DGGUHVV ' LV QRW DW DQ DGGUHVV ERXQGDU\ DFWLYH FORFN HGJH LV ULVLQJ DQG ZDLW VWDWH LV VHW WR
Figure 36.
Example of Wait States Insertion
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
111
Preliminary
AC Characteristics
Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence
tWC
tRC
tRC
tWC
CE#
OE# tOE tOEH WE# tWPH tWP tDS tDH Data
PD/30h RD
tGHWL
tACC
tOEZ tOEH
RD AAh
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH
1RWH %UHDNSRLQWV LQ ZDYHIRUPV LQGLFDWH WKDW V\VWHP PD\ DOWHUQDWHO\ UHDG DUUD\ GDWD IURP WKH QRQEXV\ EDQN ZKLOH FKHFNLQJ WKH VWDWXV RI WKH SURJUDP RU HUDVH RSHUDWLRQ LQ WKH EXV\ EDQN 7KH V\VWHP VKRXOG UHDG VWDWXV WZLFH WR HQVXUH YDOLG LQIRUPDWLRQ
Figure 37. Back-to-Back Read/Write Cycle Timings
112
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Erase and Programming Performance
3DUDPHWHU 6HFWRU (UDVH 7LPH .ZRUG .ZRUG 7\S 1RWH 0D[ 1RWH 8QLW V ([FOXGHV K SURJUDPPLQJ SULRU WR HUDVXUH 1RWH V V V V ([FOXGHV V\VWHP OHYHO RYHUKHDG 1RWH ([FOXGHV V\VWHP OHYHO RYHUKHDG 1RWH &RPPHQWV
&KLS (UDVH 7LPH :RUG 3URJUDPPLQJ 7LPH
$FFHOHUDWHG :RUG 3URJUDPPLQJ 7LPH &KLS 3URJUDPPLQJ 7LPH 1RWH $FFHOHUDWHG &KLS 3URJUDPPLQJ 7LPH -
V
1RWHV 7\SLFDO SURJUDP DQG HUDVH WLPHV DVVXPH WKH IROORZLQJ FRQGLWLRQV & 9 9&& F\FOHV $GGLWLRQDOO\ SURJUDPPLQJ W\SLFDOV DVVXPHV D FKHFNHUERDUG SDWWHUQ 8QGHU ZRUVW FDVH FRQGLWLRQV RI & 9&& 9 F\FOHV 7KH W\SLFDO FKLS SURJUDPPLQJ WLPH LV FRQVLGHUDEO\ OHVV WKDQ WKH PD[LPXP FKLS SURJUDPPLQJ WLPH OLVWHG ,Q WKH SUHSURJUDPPLQJ VWHS RI WKH (PEHGGHG (UDVH DOJRULWKP DOO ZRUGV DUH SURJUDPPHG WR K EHIRUH HUDVXUH 6\VWHPOHYHO RYHUKHDG LV WKH WLPH UHTXLUHG WR H[HFXWH WKH WZR RU IRXUEXVF\FOH VHTXHQFH IRU WKH SURJUDP FRPPDQG 6HH 7DEOH &RPPDQG 'HILQLWLRQV RQ SDJH IRU IXUWKHU LQIRUPDWLRQ RQ FRPPDQG GHILQLWLRQV 7KH GHYLFH KDV D PLQLPXP F\FOLQJ HQGXUDQFH RI F\FOHV SHU VHFWRU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
113
CosmoRAM
32Mbit (2M word x 16-bit) 64Mbit (4M word x 16-bit)
PRELIMINARY
Features
$V\QFKURQRXV 65$0 ,QWHUIDFH )DVW $FFHVV 7LPH ZRUGV 3DJH $FFHVV &DSDELOLW\ /RZ 9ROWDJH 2SHUDWLQJ &RQGLWLRQ
9'' 9 WR 9 0 9 WR 9 0 W3$$ QV PD[ W&( W$$ QV PD[
:LGH 2SHUDWLQJ 7HPSHUDWXUH
7$ & WR &
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9DULRXV 3RZHU 'RZQ PRGH
6OHHS 0ELW 3DUWLDO RU 0ELW 3DUWLDO 0 6OHHS 0ELW 3DUWLDO RU 0ELW 3DUWLDO 0
Pin Description (32M)
Pin Name Description
$ WR $ &( &( :( 2( 8% /% &/. $'9 :$,7 '4 '4 9'' 966
$GGUHVV ,QSXW $ WR $ IRU 0 $ WR $ IRU 0 &KLS (QDEOH /RZ $FWLYH &KLS (QDEOH +LJK $FWLYH :ULWH (QDEOH /RZ $FWLYH 2XWSXW (QDEOH /RZ $FWLYH 8SSHU %\WH &RQWURO /RZ $FWLYH /RZHU %\WH &RQWURO /RZ $FWLYH &ORFN ,QSXW $GGUHVV 9DOLG ,QSXW /RZ $FWLYH :DLW 6LJQDO 2XWSXW 8SSHU %\WH 'DWD ,QSXW2XWSXW /RZHU %\WH 'DWD ,QSXW2XWSXW 3RZHU 6XSSO\ *URXQG
Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
Preliminary
Functional Description
Asynchronous Operation (Page Mode)
0RGH 6WDQGE\ 'HVHOHFW 2XWSXW 'LVDEOH 1RWH 2XWSXW 'LVDEOH 1R 5HDG 5HDG 8SSHU %\WH 5HDG /RZHU %\WH 5HDG :RUG 3DJH 5HDG 1R :ULWH :ULWH 8SSHU %\WH :ULWH /RZHU %\WH :ULWH :RUG 3RZHU 'RZQ 1RWH / ; + / &( + &( + &/. ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; / + 1RWH 1RWH + / $'9 ; :( ; + 2( ; + /% ; ; + + / / /+ + + / / ; 8% ; ; + / + / /+ + / + / ; $ ; 1RWH 9DOLG 9DOLG 9DOLG 9DOLG 9DOLG 9DOLG 9DOLG 9DOLG 9DOLG ; '4 +LJK= +LJK= +LJK= +LJK= 2XWSXW 9DOLG 2XWSXW 9DOLG 1RWH ,QYDOLG ,QYDOLG ,QSXW 9DOLG ,QSXW 9DOLG +LJK= '4 +LJK= +LJK= +LJK= 2XWSXW 9DOLG +LJK= 2XWSXW 9DOLG 1RWH ,QYDOLG ,QSXW 9DOLG ,QYDOLG ,QSXW 9DOLG +LJK= :$,7 +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK= +LJK=
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
115
Preliminary
Functional Description
Synchronous Operation (Burst Mode)
0RGH 6WDQGE\ 'HVHOHFW 6WDUW $GGUHVV /DWFK 1RWH $GYDQFH %XUVW 5HDG WR 1H[W $GGUHVV 1RWH %XUVW 5HDG 6XVSHQG 1RWH $GYDQFH %XUVW :ULWH WR 1H[W $GGUHVV 1RWH %XUVW :ULWH 6XVSHQG 1RWH 7HUPLQDWH %XUVW 5HDG 7HUPLQDWH %XUVW :ULWH 3RZHU 'RZQ 1RWH / 9( 9( ; / + 9( 1RWH 9( 1RWH ; ; ; ; + / 1RWH + 1RWH + ; ; ; + ; ; ; ; &( &( + &/. ; 9( 1RWH 9( 1RWH + 9( 1RWH + ; 1RWH + ; 1RWH ; $'9 ; 3(/3 :( ; 2( ; /% ; 8% ; $ ; 9DOLG 1RWH '4 +LJK= +LJK= 1RWH 2XWSXW 9DOLG 1RWH +LJK= '4 +LJK= +LJK= 1RWH 2XWSXW 9DOLG 1RWH +LJK= ,QSXW 9DOLG 1RWH ,SXW ,QYDOLG +LJK= +LJK= +LJK= :$,7 +LJK= +LJK= 1RWH 2XWSXW 9DOLG +LJK 1RWH
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116
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
State Diagrams
Initial/Standby State
Asynchronous Operation (Page Mode)
Power Up
Synchronous Operation (Burst Mode)
Pause Time Power Down
CE2=L @M=1
CR Set
Common State
@M=0
CE2=L
Power Down
CE2=H @RP=1
CE2=H
Standby
CE2=H @RP=0
Standby (64M Only) Initial Standby State Diagram
Figure 38.
Asynchronous Operation State
CE2=CE1# = H
Standby
CE1# = L & WE# = L
CE1# = L
CE1# = H
CE1# = L & OE# = L
CE1# = H
Output Disable
CE1# = H
WE# = H WE# = L Byte Control OE# = H
OE# = L
Write
Byte Control @OE# = L
Read
Address Change or Byte Control
Figure 39.
Asynchronous Operation State Diagram
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
117
Preliminary
Synchronous Operation State
CE2 = CE1# = H
Standby
CE1# = H CE1# = H
CE1# = H
CE1# = H
Write Suspend
WE# = H WE# = L CE1# = L ADV# Low Pulse & WE# = L CE1# = L ADV# Low Pulse & OE# = L OE# = H
Read Suspend
OE# = L
ADV# Low Pulse
Write
ADV# Low Pulse (@BL = 8 or 16, and after burst operation is completed)
Read
ADV# Low Pulse
Figure 40.
1RWHV
Synchronous Operation Diagram
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Functional Description
7KLV GHYLFH VXSSRUWV DV\QFKURQRXV SDJH UHDG QRUPDO ZULWH RSHUDWLRQ DQG V\Q FKURQRXV EXUVW UHDG EXUVW ZULWH RSHUDWLRQ IRU IDVWHU PHPRU\ DFFHVV DQG IHDWXUHV WKUHH NLQGV RI SRZHU GRZQ PRGHV IRU SRZHU VDYLQJ DV D XVHU FRQILJ XUDEOH RSWLRQ
Power-up
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Configuration Register
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CR Set Sequence
7KH &5 6HW UHTXLUHV WRWDO UHDGZULWH RSHUDWLRQV ZLWK XQLTXH DGGUHVV %HWZHHQ HDFK UHDGZULWH RSHUDWLRQ UHTXLUHV WKH GHYLFH WR EH LQ VWDQGE\ PRGH 7KH IROORZ LQJ WDEOH VKRZV WKH GHWDLO VHTXHQFH
Cycle # Operation Address Data
VW QG
5HDG :ULWH
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5HDG 'DWD 5'D 5'D
118
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Cycle #
Operation
Address
Data
UG WK WK WK
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
119
Preliminary
Address Key
7KH DGGUHVV NH\ KDV WKH IROORZLQJ IRUPDW
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1RWHV
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120
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Power Down
7KH 3RZHU 'RZQ LV ORZ SRZHU LGOH VWDWH FRQWUROOHG E\ &( &( /RZ GULYHV WKH GHYLFH LQ SRZHU GRZQ PRGH DQG PDLQWDLQV ORZ SRZHU LGOH VWDWH DV ORQJ DV &( LV NHSW /RZ &( +LJK UHVXPHV WKH GHYLFH IURP SRZHU GRZQ PRGH 7KHVH GHYLFHV KDYH WKUHH SRZHU GRZQ PRGH 7KHVH FDQ EH SURJUDPPHG E\ VHULHV RI UHDGZULWH RSHUDWLRQV (DFK PRGH KDV IROORZLQJ IHDWXUHV
32M Mode Data Retention Size Retention Address Mode 64M Data Retention Size Retention Address
6OHHS GHIDXOW 0 3DUWLDO 0 3DUWLDO
1R 0 ELW 0 ELW
1$ K WR ))))K K WR ))))K
6OHHS GHIDXOW 0 3DUWLDO 0 3DUWLDO
1R 0 ELW 0 ELW
1$ K WR ))))K K WR )))))K
7KH GHIDXOW VWDWH LV 6OHHS DQG LW LV WKH ORZHVW SRZHU FRQVXPSWLRQ EXW DOO GDWD ZLOO EH ORVW RQFH &( LV EURXJKW WR /RZ IRU 3RZHU 'RZQ ,W LV QRW UHTXLUHG WR SURJUDP WR 6OHHS PRGH DIWHU SRZHUXS 0 VXSSRUWV 5HVHW WR 3DJH 53 PRGH :KHQ 53 3RZHU 'RZQ FRPSUHKHQGV D IXQFWLRQ WR UHVHW WKH GHYLFH WR GHIDXOW FRQILJXUDWLRQ DV\QFKURQRXV PRGH $IWHU UHVXPLQJ IURP SRZHU GRZQ PRGH WKH GHYLFH LV EDFN LQ GHIDXOW FRQILJXUDWLRQV 7KLV LV HIIHFWLYH RQO\ ZKHQ 36 LV VHW RQ 6OHHS PRGH :KHQ 3DUWLDO PRGH LV VH OHFWHG 53 LV QRW HIIHFWLYH
Burst Read/Write Operation
6\QFKURQRXV EXUVW UHDGZULWH RSHUDWLRQ SURYLGHV IDVWHU PHPRU\ DFFHVV WKDW V\Q FKURQL]HG WR PLFURFRQWUROOHU RU V\VWHP EXV IUHTXHQF\ &RQILJXUDWLRQ 5HJLVWHU 6HW LV UHTXLUHG WR SHUIRUP EXUVW UHDG ZULWH RSHUDWLRQ DIWHU SRZHUXS 2QFH &5 6HW VHTXHQFH LV SHUIRUPHG WR VHOHFW V\QFKURQRXV EXUVW PRGH WKH GHYLFH LV FRQILJ XUHG WR V\QFKURQRXV EXUVW UHDGZULWH RSHUDWLRQ PRGH ZLWK FRUUHVSRQGLQJ 5/ DQG %/ WKDW LV VHW WKURXJK &5 6HW VHTXHQFH WRJHWKHU ZLWK RSHUDWLRQ PRGH ,Q RUGHU WR SHUIRUP V\QFKURQRXV EXUVW UHDG ZULWH RSHUDWLRQ LW LV UHTXLUHG WR FRQWURO QHZ VLJQDOV &/. $'9 DQG :$,7 WKDW /RZ 3RZHU 65$0V GRQW KDYH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
121
Preliminary
CLK ADDRESS ADV# CE1# Valid
OE# High WE# DQ High-Z RL Q1 BL WAIT# High-Z Q2 QBL
Figure 41. Burst Read Operation
CLK ADDRESS ADV# CE1# High OE# WE# DQ High-Z RL-1 D1 BL WAIT# High-Z D2 DBL Valid
Figure 42.
Burst Write Operation
CLK Input Function
7KH &/. LV LQSXW VLJQDO WR V\QFKURQL]H PHPRU\ WR PLFURFRQWUROOHU RU V\VWHP EXV IUHTXHQF\ GXULQJ V\QFKURQRXV EXUVW UHDG ZULWH RSHUDWLRQ 7KH &/. LQSXW LQFUH PHQWV GHYLFH LQWHUQDO DGGUHVV FRXQWHU DQG WKH YDOLG HGJH RI &/. LV UHIHUUHG IRU ODWHQF\ FRXQWV IURP DGGUHVV ODWFK EXUVW ZULWH GDWD ODWFK DQG EXUVW UHDG GDWD RXW 'XULQJ V\QFKURQRXV RSHUDWLRQ PRGH &/. LQSXW PXVW EH VXSSOLHG H[FHSW IRU VWDQGE\ VWDWH DQG SRZHU GRZQ VWDWH &/. LV GRQW FDUH GXULQJ DV\QFKURQRXV RSHUDWLRQ
122
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
ADV# Input Function
7KH $'9 LV LQSXW VLJQDO WR LQGLFDWH YDOLG DGGUHVV SUHVHQFH RQ DGGUHVV LQSXWV ,W LV DSSOLFDEOH WR V\QFKURQRXV RSHUDWLRQ DV ZHOO DV DV\QFKURQRXV RSHUDWLRQ $'9 LQSXW LV DFWLYH GXULQJ &( / DQG &( + GLVDEOHV $'9 LQSXW $OO DGGUHVVHV DUH GHWHUPLQHG RQ WKH SRVLWLYH HGJH RI $'9 'XULQJ V\QFKURQRXV EXUVW UHDGZULWH RSHUDWLRQ $'9 + GLVDEOHV DOO DGGUHVV LQ SXWV 2QFH $'9 LV EURXJKW WR +LJK DIWHU YDOLG DGGUHVV ODWFK LW LV LQKLELWHG WR EULQJ $'9 /RZ XQWLO WKH HQG RI EXUVW RU XQWLO EXUVW RSHUDWLRQ LV WHUPLQDWHG $'9 /RZ SXOVH LV PDQGDWRU\ IRU V\QFKURQRXV EXUVW UHDGZULWH RSHUDWLRQ PRGH WR ODWFK WKH YDOLG DGGUHVV LQSXW 'XULQJ DV\QFKURQRXV RSHUDWLRQ $'9 + DOVR GLVDEOHV DOO DGGUHVV LQSXWV $'9 FDQ EH WLHG WR /RZ GXULQJ DV\QFKURQRXV RSHUDWLRQ DQG LW LV QRW QHFHVVDU\ WR FRQ WURO $'9 WR +LJK
WAIT# Output Function
7KH :$,7 LV RXWSXW VLJQDO WR LQGLFDWH GDWD EXV VWDWXV ZKHQ WKH GHYLFH LV RSHU DWLQJ LQ V\QFKURQRXV EXUVW PRGH 'XULQJ EXUVW UHDG RSHUDWLRQ :$,7 RXWSXW LV HQDEOHG DIWHU VSHFLILHG WLPH GXUD WLRQ IURP 2( / RU &( / ZKLFKHYHU RFFXUV ODVW :$,7 RXWSXW /RZ LQGLFDWHV GDWD RXW DW QH[W FORFN F\FOH LV LQYDOLG DQG :$,7 RXWSXW EHFRPHV +LJK RQH FORFN F\FOH SULRU WR YDOLG GDWD RXW 'XULQJ 2( UHDG VXVSHQG :$,7 RXWSXW GRHVQW LQGLFDWH GDWD EXV VWDWXV EXW FDUULHV WKH VDPH OHYHO IURP SUHYLRXV FORFN F\FOH NHSW +LJK H[FHSW IRU UHDG VXVSHQG RQ WKH ILQDO GDWD RXWSXW ,I ILQDO UHDG GDWD RXW LV VXVSHQGHG :$,7 RXWSXW EHFRPH KLJK LPSHGDQFH DIWHU VSHFLILHG WLPH GXUDWLRQ IURP 2( + ,Q FDVH RI FRQWLQXRXV EXUVW UHDG RSHUDWLRQ RI 0 DQ DGGLWLRQDO RXWSXW GHOD\ PD\ RFFXU ZKHQ D EXUVW VHTXHQFH FURVVHV LWV GHYLFHURZ ERXQGDU\ 7KH :$,7 RXW SXW LQGLFDWHV WKLV GHOD\ 5HIHU WR WKH %XUVW /HQJWK VHFWLRQ IRU WKH DGGLWLRQDO GHOD\ F\FOHV LQ GHWDLOV 'XULQJ EXUVW ZULWH RSHUDWLRQ :$,7 RXWSXW LV HQDEOHG WR +LJK OHYHO DIWHU VSHFL ILHG WLPH GXUDWLRQ IURP :( / RU &( / ZKLFKHYHU RFFXUV ODVW DQG NHSW +LJK IRU HQWLUH ZULWH F\FOHV LQFOXGLQJ :( ZULWH VXVSHQG 7KH DFWXDO ZULWH GDWD ODWFK LQJ VWDUWV RQ WKH DSSURSULDWH FORFN HGJH ZLWK UHVSHFW WR 9DOLG &ORFN (GJH 5HDG /DWHQF\ DQG %XUVW /HQJWK 'XULQJ :( ZULWH VXVSHQG :$,7 RXWSXW GRHVQW LQ GLFDWH GDWD EXV VWDWXV EXW FDUULHV WKH VDPH OHYHO IURP SUHYLRXV FORFN F\FOH NHSW +LJK H[FHSW IRU ZULWH VXVSHQG RQ WKH ILQDO GDWD LQSXW ,I ILQDO ZULWH GDWD LQ LV VXV SHQGHG :$,7 RXWSXW EHFRPH KLJK LPSHGDQFH DIWHU VSHFLILHG WLPH GXUDWLRQ IURP :( + 7KH EXUVW ZULWH RSHUDWLRQ RI 0 DQG WKH ERWK EXUVW UHDGZULWH RSHUDWLRQ RI 0 DUH DOZD\V VWDUWHG DIWHU IL[HG ODWHQF\ ZLWK UHVSHFW WR 5HDG /DWHQF\ VHW LQ &5 :KHQ WKH GHYLFH LV RSHUDWLQJ LQ DV\QFKURQRXV PRGH :$,7 +LJK ,PSHGDQFH RXWSXW LV DOZD\V LQ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
123
Preliminary
Latency
5HDG /DWHQF\ 5/ LV WKH QXPEHU RI FORFN F\FOHV EHWZHHQ WKH DGGUHVV EHLQJ ODWFKHG DQG ILUVW UHDG GDWD EHFRPLQJ DYDLODEOH GXULQJ V\QFKURQRXV EXUVW UHDG RS HUDWLRQ ,W LV VHW WKURXJK &5 6HW VHTXHQFH DIWHU SRZHUXS 2QFH VSHFLILF 5/ LV VHW WKURXJK &5 6HW VHTXHQFH ZULWH ODWHQF\ WKDW LV WKH QXPEHU RI FORFN F\FOHV EH WZHHQ DGGUHVV EHLQJ ODWFKHG DQG ILUVW ZULWH GDWD EHLQJ ODWFKHG LV DXWRPDWLFDOO\ VHW WR 5/7KH EXUVW RSHUDWLRQ LV DOZD\V VWDUWHG DIWHU IL[HG ODWHQF\ ZLWK UHVSHFW WR 5HDG /DWHQF\ VHW LQ &5 5/ LV DYDLODEOH RQO\ IRU 0
CLK 0 ADDRESS ADV# CE1# OE# or WE# RL=3 DQ [Out] WAIT# DQ [In] WAIT# High-Z RL=4 DQ [Out] WAIT# DQ [In] WAIT# High-Z RL=5 DQ [Out] WAIT# DQ [In] WAIT# High-Z RL=6 DQ [Out] WAIT# DQ [In] WAIT# High-Z High-Z D1 D2 D3 Q1 Q2 High-Z D1 D2 D3 D4 Q1 Q2 Q3 High-Z D1 D2 D3 D4 D5 Q1 Q2 Q3 Q4 High-Z D1 D2 D3 D4 D5 D5 Q1 Q2 Q3 Q4 Q5 Valid 1 2 3 4 5 6
Figure 43. Read Latency Diagram
124
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Address Latch by ADV#
7KH $'9 LQGLFDWHV YDOLG DGGUHVV SUHVHQFH RQ DGGUHVV LQSXWV 'XULQJ V\QFKUR QRXV EXUVW UHDGZULWH RSHUDWLRQ PRGH DOO WKH DGGUHVV DUH GHWHUPLQHG RQ WKH SRVLWLYH HGJH RI $'9 ZKHQ &( / 7KH VSHFLILHG PLQLPXP YDOXH RI $'9 / VHWXS WLPH DQG KROG WLPH DJDLQVW YDOLG HGJH RI FORFN ZKHUH 5/ FRXQW EHJLQ PXVW EH VDWLVILHG IRU DSSURSULDWH 5/ FRXQWV 9DOLG DGGUHVV PXVW EH GHWHUPLQHG ZLWK VSHFLILHG VHWXS WLPH DJDLQVW HLWKHU WKH QHJDWLYH HGJH RI $'9 RU QHJDWLYH HGJH RI &( ZKLFKHYHU FRPHV ODWH $QG WKH GHWHUPLQHG YDOLG DGGUHVV PXVW QRW EH FKDQJHG GXULQJ $'9 / SHULRG
Burst Length
%XUVW /HQJWK LV WKH QXPEHU RI ZRUG WR EH UHDG RU ZULWH GXULQJ V\QFKURQRXV EXUVW UHDGZULWH RSHUDWLRQ DV WKH UHVXOW RI D VLQJOH DGGUHVV ODWFK F\FOH ,W FDQ EH VHW RQ ZRUGV ERXQGDU\ RU FRQWLQXRXV IRU HQWLUH DGGUHVV WKURXJK &5 6HW VHTXHQFH 7KH EXUVW W\SH LV VHTXHQWLDO WKDW LV LQFUHPHQWDO GHFRGLQJ VFKHPH ZLWKLQ D ERXQG DU\ DGGUHVV 6WDUWLQJ IURP LQLWLDO DGGUHVV EHLQJ ODWFKHG GHYLFH LQWHUQDO DGGUHVV FRXQWHU DVVLJQ WR WKH SUHYLRXV DGGUHVV XQWLO UHDFKLQJ WKH HQG RI ERXQGDU\ DG GUHVV DQG WKHQ ZUDS URXQG WR OHDVW VLJQLILFDQW DGGUHVV $IWHU FRPSOHWLQJ UHDG GDWD RXW RU ZULWH GDWD ODWFK IRU WKH VHW EXUVW OHQJWK RSHUDWLRQ DXWRPDWLFDOO\ HQGHG H[FHSW IRU FRQWLQXRXV EXUVW OHQJWK :KHQ FRQWLQXRXV EXUVW OHQJWK LV VHW UHDGZULWH LV HQGOHVV XQOHVV LW LV WHUPLQDWHG E\ WKH SRVLWLYH HGJH RI &( 'XULQJ FRQWLQXRXV EXUVW UHDG RI 0 DQ DGGLWLRQDO RXWSXW GHOD\ PD\ RFFXU ZKHQ D EXUVW VHTXHQFH FURVV LWV GHYLFHURZ ERXQGDU\ 7KLV LV WKH FDVH ZKHQ $ WR $ RI VWDUWLQJ DGGUHVV LV HLWKHU 'K (K RU )K DV VKRZQ LQ WKH IROORZLQJ WDEOH 7KH :$,7 VLJQDO LQGLFDWHV WKLV GHOD\ 7KH 0 GHYLFH KDV QR DGGLWLRQDO RXWSXW GHOD\
Read Address Sequence BL = 8 BL = 16 Continuous
Start Address (A6-A0)
K K K K &K 'K (K )K
&)% '()& ()' )$(
() ) ) ) &)% '()& ()' )(
&'() '():$,7 ():$,7:$,7 ):$,7:$,7:$,7
1RWH 5HDG DGGUHVV LQ +H[DGHFLPDO
Single Write
6LQJOH :ULWH LV V\QFKURQRXV ZULWH RSHUDWLRQ ZLWK %XUVW /HQJWK 7KH GHYLFH FDQ EH FRQILJXUHG HLWKHU WR %XUVW 5HDG 6LQJOH :ULWH RU WR %XUVW 5HDG %XUVW :ULWH WKURXJK &5 VHW VHTXHQFH 2QFH WKH GHYLFH LV FRQILJXUHG WR %XUVW 5HDG 6LQJOH :ULWH PRGH WKH EXUVW OHQJWK IRU V\QFKURQRXV ZULWH RSHUDWLRQ LV DOZD\V IL[HG UHJDUGOHVV RI %/ YDOXHV VHW LQ &5 ZKLOH EXUVW OHQJWK IRU UHDG LV LQ DFFRU GDQFH ZLWK %/ YDOXHV VHW LQ &5
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
125
Preliminary
Write Control
7KH GHYLFH KDV WZR W\SHV RI :( VLJQDO FRQWURO PHWKRG :( /HYHO &RQWURO DQG :( 6LQJOH &ORFN 3XOVH &RQWURO IRU V\QFKURQRXV ZULWH RSHUDWLRQ ,W LV FRQILJ XUHG WKURXJK &5 VHW VHTXHQFH
CLK 0 ADDRESS ADV# CE1# WE# Level Control WE# DQ [In] WAIT# tWLTH High-Z tWLD D1 D2 D3 D4 RL=5 Valid 1 2 3 4 5 6
WE# Single Clock Pulse Control tWSCK WE# tCKWH DQ [In] WAIT# tCLTH tWLTH High-Z D1 D2 D3 D4
Figure 44. Write Controls
Burst Read Suspend
%XUVW UHDG RSHUDWLRQ FDQ EH VXVSHQGHG E\ 2( +LJK SXOVH 'XULQJ EXUVW UHDG RS HUDWLRQ 2( EURXJKW WR +LJK VXVSHQGV EXUVW UHDG RSHUDWLRQ 2QFH 2( LV EURXJKW WR +LJK ZLWK WKH VSHFLILHG VHW XS WLPH DJDLQVW FORFN ZKHUH WKH GDWD EHLQJ VXVSHQGHG WKH GHYLFH LQWHUQDO FRXQWHU LV VXVSHQGHG DQG WKH GDWD RXWSXW EH FRPH KLJK LPSHGDQFH DIWHU VSHFLILHG WLPH GXUDWLRQ ,W LV LQKLELWHG WR VXVSHQG WKH ILUVW GDWD RXW DW WKH EHJLQQLQJ RI EXUVW UHDG 2( EURXJKW WR /RZ UHVXPHV EXUVW UHDG RSHUDWLRQ 2QFH 2( LV EURXJKW WR /RZ GDWD RXWSXW EHFRPH YDOLG DIWHU VSHFLILHG WLPH GXUDWLRQ DQG LQWHUQDO DGGUHVV FRXQWHU LV UHDFWLYDWHG 7KH ODVW GDWD RXW EHLQJ VXVSHQGHG DV WKH UHVXOW RI 2( + DQG ILUVW GDWD RXW DV WKH UHVXOW RI 2( / DUH IURP WKH VDPH DGGUHVV ,Q RUGHU WR JXDUDQWHH WR RXWSXW ODVW GDWD EHIRUH VXVSHQVLRQ DQG ILUVW GDWD DIWHU UHVXPSWLRQ WKH VSHFLILHG PLQLPXP YDOXH RI 2( / KROG WLPH DQG VHWXS WLPH DJDLQVW FORFN HGJH PXVW EH VDWLVILHG UHVSHFWLYHO\
126
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
CLK tCKOH tOSCK OE# tCKOH tOSCK
tAC DQ tCKTV WAIT# Q1 tCKQX
tOHZ Q2 tOLZ
tAC
tAC Q2 tCKQX
tAC Q3 tCKQX Q4
Figure 45. Burst Read Suspend Diagram
Burst Write Suspend
%XUVW ZULWH RSHUDWLRQ FDQ EH VXVSHQGHG E\ :( +LJK SXOVH 'XULQJ EXUVW ZULWH RSHUDWLRQ :( EURXJKW WR +LJK VXVSHQGV EXUVW ZULWH RSHUDWLRQ 2QFH :( LV EURXJKW WR +LJK ZLWK WKH VSHFLILHG VHW XS WLPH DJDLQVW FORFN ZKHUH WKH GDWD EHLQJ VXVSHQGHG GHYLFH LQWHUQDO FRXQWHU LV VXVSHQGHG GDWD LQSXW LV LJQRUHG ,W LV LQ KLELWHG WR VXVSHQG WKH ILUVW GDWD LQSXW DW WKH EHJLQQLQJ RI EXUVW ZULWH :( EURXJKW WR /RZ UHVXPHV EXUVW ZULWH RSHUDWLRQ 2QFH :( LV EURXJKW WR /RZ GDWD LQSXW EHFRPH YDOLG DIWHU VSHFLILHG WLPH GXUDWLRQ DQG LQWHUQDO DGGUHVV FRXQWHU LV UHDFWLYDWHG 7KH ZULWH DGGUHVV RI WKH F\FOH ZKHUH GDWD EHLQJ VXV SHQGHG DQG WKH ILUVW ZULWH DGGUHVV DV WKH UHVXOW RI :( / DUH WKH VDPH DGGUHVV ,Q RUGHU WR JXDUDQWHH WR ODWFK WKH ODVW GDWD LQSXW EHIRUH VXVSHQVLRQ DQG ILUVW GDWD LQSXW DIWHU UHVXPSWLRQ WKH VSHFLILHG PLQLPXP YDOXH RI :( / KROG WLPH DQG VHWXS WLPH DJDLQVW FORFN HGJH PXVW EH VDWLVILHG UHVSHFWLYHO\ %XUVW ZULWH VXVSHQG IXQFWLRQ LV DYDLODEOH ZKHQ WKH GHYLFH LV RSHUDWLQJ LQ :( OHYHO FRQWUROOHG EXUVW ZULWH RQO\
CLK tCKWH tWSCK WE# tCKWH tWSCK
tDSCK DQ D1 tDHCK WAIT# High D2
tDSCK D2
tDSCK D3
tDSCK D4
tDHCK
tDHCK
Figure 46.
Burst Write Suspend Diagram
Burst Read Termination
%XUVW UHDG RSHUDWLRQ FDQ EH WHUPLQDWHG E\ &( EURXJKW WR +LJK ,I %/ LV VHW RQ &RQWLQXRXV EXUVW UHDG RSHUDWLRQ LV FRQWLQXHG HQGOHVV XQOHVV WHUPLQDWHG E\
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
127
Preliminary
&( + ,W LV LQKLELWHG WR WHUPLQDWH EXUVW UHDG EHIRUH ILUVW GDWD RXW LV FRPSOHWHG ,Q RUGHU WR JXDUDQWHH ODVW GDWD RXWSXW WKH VSHFLILHG PLQLPXP YDOXH RI &( / KROG WLPH IURP FORFN HGJH PXVW EH VDWLVILHG $IWHU WHUPLQDWLRQ WKH VSHFLILHG PLQ LPXP UHFRYHU\ WLPH LV UHTXLUHG WR VWDUW QHZ DFFHVV
CLK ADDRESS ADV# tCKCLH CE1# tCKOH OE# WAIT# DQ tAC Q1 Q2 tCHTZ tCKQX High-Z tOHZ tCHZ tTRB Valid
Figure 47.
Burst Read Termination Diagram
Burst Write Termination
%XUVW ZULWH RSHUDWLRQ FDQ EH WHUPLQDWHG E\ &( EURXJKW WR +LJK ,I %/ LV VHW RQ &RQWLQXRXV EXUVW ZULWH RSHUDWLRQ LV FRQWLQXHG HQGOHVV XQOHVV WHUPLQDWHG E\ &( + ,W LV LQKLELWHG WR WHUPLQDWH EXUVW ZULWH EHIRUH ILUVW GDWD LQ LV FRPSOHWHG ,Q RUGHU WR JXDUDQWHH ODVW ZULWH GDWD EHLQJ ODWFKHG WKH VSHFLILHG PLQLPXP YDOXHV RI &( / KROG WLPH IURP FORFN HGJH PXVW EH VDWLVILHG $IWHU WHUPLQDWLRQ WKH VSHFLILHG PLQLPXP UHFRYHU\ WLPH LV UHTXLUHG WR VWDUW QHZ DFFHVV
CLK ADDRESS ADV# tCKCLH CE1# tCKWH WE# WAIT# DQ tCHTZ tDSCK D1 tDHCK tDSCK D2 tDHCK High-Z tCHCK tTRB Valid
Figure 48.
Burst Write Termination Diagram
128
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Absolute Maximum Ratings
Item Symbol Value Unit
9ROWDJH RI 9'' 6XSSO\ 5HODWLYH WR 966 9ROWDJH DW $Q\ 3LQ 5HODWLYH WR 966 6KRUW &LUFXLW 2XWSXW &XUUHQW 6WRUDJH WHPSHUDWXUH
9'' 9,1 9287 ,287 767*
WR WR WR
9 9 P$ &
:$51,1* 6HPLFRQGXFWRU GHYLFHV FDQ EH SHUPDQHQWO\ GDPDJHG E\ DSSOLFDWLRQ RI VWUHVV YROWDJH FXUUHQW WHPSHUDWXUH HWF LQ H[FHVV RI DEVROXWH PD[LPXP UDWLQJV 'R QRW H[FHHG WKHVH UDWLQJV
Recommended Operating Conditions (See Warning Below)
32M Parameter Symbol Min Max Min 64M Max Unit
6XSSO\ 9ROWDJH +LJK /HYHO ,QSXW 9ROWDJH 1RWH +LJK /HYHO ,QSXW 9ROWDJH 1RWH $PELHQW 7HPSHUDWXUH
1RWHV
9'' 966 9,+ 9,/ 7$
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9 9 9 9 &
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:$51,1* 5HFRPPHQGHG RSHUDWLQJ FRQGLWLRQV DUH QRUPDO RSHUDWLQJ UDQJHV IRU WKH VHPLFRQGXFWRU GHYLFH $OO WKH GH YLFHV HOHFWULFDO FKDUDFWHULVWLFV DUH ZDUUDQWHG ZKHQ RSHUDWHG ZLWKLQ WKHVH UDQJHV $OZD\V XVH VHPLFRQGXFWRU GHYLFHV ZLWKLQ WKH UHFRPPHQGHG RSHUDWLQJ FRQGLWLRQV 2SHUDWLRQ RXWVLGH WKHVH UDQJHV PD\ DGYHUVHO\ DIIHFW UHOLDELOLW\ DQG FRXOG UHVXOW LQ GHYLFH IDLOXUH 1R ZDUUDQW\ LV PDGH ZLWK UHVSHFW WR XVHV RSHUDWLQJ FRQGLWLRQV RU FRPELQDWLRQV QRW UHSUHVHQWHG RQ WKH GDWD VKHHW
Package Pin Capacitance
7HVW FRQGLWLRQV 7$
Symbol
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0+]
Test Setup Typ Max Unit
Description
&,1 &,1 &,2
$GGUHVV ,QSXW &DSDFLWDQFH &RQWURO ,QSXW &DSDFLWDQFH 'DWD ,QSXW2XWSXW &DSDFLWDQFH
9,1 9,1 9,2
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
129
Preliminary
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
0 3DUDPHWHU 6\PERO 7HVW &RQGLWLRQV 0LQ ,QSXW /HDNDJH &XUUHQW 2XWSXW /HDNDJH &XUUHQW 2XWSXW +LJK 9ROWDJH /HYHO 2XWSXW /RZ 9ROWDJH /HYHO ,/, ,/2 92+ 92/ ,''36 9'' 3RZHU 'RZQ &XUUHQW ,''3 ,''3 ,''3 ,''6 9'' 9'' PD[ 9,1 LQFOXGLQJ &/. &( &( 9,+ 9,+ RU 9,/ 7$ & 7$ & 9'' 9'' PD[ 9,1 9,+ RU 9,/ &( 9 9,1 9287 9'' ,2/ 966 WR 9'' 966 WR 9'' 2XWSXW 'LVDEOH 9''PLQ ,2+ P$ 6/((3 0 3DUWLDO 0 3DUWLDO 0 3DUWLDO P$ 0D[ 0LQ 0D[ $ 0 8QLW

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7%' 7%'
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9'' 9'' PD[ 9,1 9,+ RU 9,/ &( 9,/ DQG &( ,287 P$
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9'' 9'' PD[ 9,1 9,+ RU 9,/ &( 9,/ DQG &( 9,+ ,287 P$ W35& PLQ 9'' 9'' PD[ 9,1 9,+ RU 9,/ &( 9,/ DQG &( 9,+ W&. W&. PLQ %/ &RQWLQXRXV ,287 P$
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1RWHV
$OO YROWDJHV DUH UHIHUHQFHG WR 966 '& &KDUDFWHULVWLFV DUH PHDVXUHG DIWHU IROORZLQJ 32:(583 WLPLQJ ,287 GHSHQGV RQ WKH RXWSXW ORDG FRQGLWLRQV
130
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
5HDG &\FOH 7LPH &( 2( $FFHVV 7LPH $FFHVV 7LPH
W5& W&( W2( W$$ W$9 W%$ W3$$ W35& W2+ W&/= W2/= W%/= W&+= W2+= W%+= W$6& W$62 W93/ W93+ W$69 W$+9 W$; +LJK +LJK W&+$+ W2+$+ W:+2/ W&3

QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV

$GGUHVV $FFHVV 7LPH $'9 /% $FFHVV 7LPH 8% $FFHVV 7LPH

3DJH $GGUHVV $FFHVV 7LPH 3DJH 5HDG &\FOH 7LPH 2XWSXW 'DWD +ROG 7LPH &( 2( /% &( 2( /% /RZ WR 2XWSXW /RZ= /RZ WR 2XWSXW /RZ= 8% /RZ WR 2XWSXW /RZ=
+LJK WR 2XWSXW +LJK= +LJK WR 2XWSXW +LJK= 8% +LJK WR 2XWSXW +LJK= /RZ /RZ
$GGUHVV 6HWXS 7LPH WR &( $GGUHVV 6HWXS 7LPH WR 2( $'9 $'9 /RZ 3XOVH :LGWK +LJK 3XOVH :LGWK

$GGUHVV 6HWXS 7LPH WR $'9 +LJK $GGUHVV +ROG 7LPH IURP $'9 $GGUHVV ,QYDOLG 7LPH $GGUHVV +ROG 7LPH IURP &( $GGUHVV +ROG 7LPH IURP 2( :( &( +LJK WR 2( +LJK

/RZ 7LPH IRU 5HDG
+LJK 3XOVH :LGWK
1RWHV
0D[LPXP YDOXH LV DSSOLFDEOH LI &( LV NHSW DW /RZ ZLWKRXW FKDQJH RI DGGUHVV LQSXW RI $ WR $ $GGUHVV VKRXOG QRW EH FKDQJHG ZLWKLQ PLQLPXP W5& 7KH RXWSXW ORDG S) ZLWK RKP WHUPLQDWLRQ WR 9'' 9
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
131
Preliminary
7KH RXWSXW ORDG S) ZLWKRXW DQ\ RWKHU ORDG $SSOLFDEOH WR $ WR $ ZKHQ &( LV NHSW DW /RZ LV NHSW DW /RZ IRU WKH SDJH DGGUHVV DFFHVV VWD\V /RZ &( RU $'9 PXVW EH EURXJKW WR +LJK ZLWKLQ V ,Q RWKHU $SSOLFDEOH RQO\ WR $ $ DQG $ ZKHQ &(
,Q FDVH 3DJH 5HDG &\FOH LV FRQWLQXHG ZLWK NHHSLQJ &( ZRUGV 3DJH 5HDG &\FOH PXVW EH FORVHG ZLWKLQ V W93/ LV VSHFLILHG IURP WKH QHJDWLYH HGJH RI HLWKHU &( HTXDO RU JUHDWHU WKDQ W5& IRU HDFK DFFHVV W5&PLQ DQG W35&PLQ PXVW EH VDWLVILHG
ZKLFKHYHU FRPHV ODWH 7KH VXP RI W93/ DQG W93+ PXVW EH
$SSOLFDEOH WR DGGUHVV DFFHVV ZKHQ DW OHDVW WZR RI DGGUHVV LQSXWV DUH VZLWFKHG IURP SUHYLRXV VWDWH ,I DFWXDO YDOXH RI W:+2/ LV VKRUWHU WKDQ VSHFLILHG PLQLPXP YDOXHV WKH DFWXDO W$$ RI IROORZLQJ 5HDG PD\ EHFRPH ORQJHU E\ WKH DPRXQW RI VXEWUDFWLQJ DFWXDO YDOXH IURP VSHFLILHG PLQLPXP YDOXH
132
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Write Operation
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
:ULWH &\FOH 7LPH $GGUHVV 6HWXS 7LPH $'9 $'9 /RZ 3XOVH :LGWK +LJK 3XOVH :LGWK +LJK +LJK
W:& W$6 W93/ W93+ W$69 W$+9 W&: W:3 W%: W%6 W%+ W:5& W:5 W&3 W:+3 W%+3 W'6 W'+ /RZ 6HWXS 7LPH IRU :ULWH W2+&/ W2(6 W%:2

QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV

$GGUHVV 6HWXS 7LPH WR $'9 $GGUHVV +ROG 7LPH IURP $'9 &( :( /% /% /% &( :ULWH 3XOVH :LGWK :ULWH 3XOVH :LGWK 8% 8% 8% :ULWH 3XOVH :LGWK

%\WH 0DVN 6HWXS 7LPH %\WH 0DVN +ROG 7LPH
:ULWH 5HFRYHU\ 7LPH
:ULWH 5HFRYHU\ 7LPH &( :( /% +LJK 3XOVH :LGWK +LJK 3XOVH :LGWK 8% +LJK 3XOVH :LGWK
'DWD 6HWXS 7LPH 'DWD +ROG 7LPH 2( 2( /% +LJK WR &(

+LJK WR $GGUHVV 6HWXS 7LPH IRU :ULWH 8% :ULWH 3XOVH 2YHUODS
1RWHV
0D[LPXP YDOXH LV DSSOLFDEOH LI &(
LV NHSW DW /RZ ZLWKRXW DQ\ DGGUHVV FKDQJH 8% ZKLFKHYHU RFFXUV ODVW
0LQLPXP YDOXH PXVW EH HTXDO RU JUHDWHU WKDQ WKH VXP RI ZULWH SXOVH W&: W:3 RU W%: DQG ZULWH UHFRYHU\ WLPH W:5 :ULWH SXOVH LV GHILQHG IURP +LJK WR /RZ WUDQVLWLRQ RI &( :( RU /% W93/ LV VSHFLILHG IURP WKH QHJDWLYH HGJH RI HLWKHU &( RU $'9 HTXDO RU JUHDWHU WKDQ W:& IRU HDFK DFFHVV ZKLFKHYHU FRPHV ODWH 7KH VXP RI W93/ DQG W93+ PXVW EH RU :( RU :( ZKLFKHYHU ZKLFKHYHU
$SSOLFDEOH IRU E\WH PDVN RQO\ %\WH PDVN VHWXS WLPH LV GHILQHG WR WKH +LJK WR /RZ WUDQVLWLRQ RI &( RFFXUV ODVW $SSOLFDEOH IRU E\WH PDVN RQO\ %\WH PDVN KROG WLPH LV GHILQHG IURP WKH /RZ WR +LJK WUDQVLWLRQ RI &( RFFXUV ILUVW :ULWH UHFRYHU\ LV GHILQHG IURP /RZ WR +LJK WUDQVLWLRQ RI &( :( RU /%
8% ZKLFKHYHU RFFXUV ILUVW
,I 2( LV /RZ DIWHU PLQLPXP W2+&/ UHDG F\FOH LV LQLWLDWHG ,Q RWKHU ZRUGV 2( PXVW EH EURXJKW WR +LJK ZLWKLQ QV DIWHU &( LV EURXJKW WR /RZ 2QFH UHDG F\FOH LV LQLWLDWHG QHZ ZULWH SXOVH VKRXOG EH LQSXW DIWHU PLQLPXP W5& LV PHW ,I 2( LV /RZ DIWHU QHZ DGGUHVV LQSXW UHDG F\FOH LV LQLWLDWHG ,Q RWKHU ZRUG 2( PXVW EH EURXJKW WR +LJK DW WKH VDPH WLPH RU EHIRUH QHZ DGGUHVV YDOLG 2QFH UHDG F\FOH LV LQLWLDWHG QHZ ZULWH SXOVH VKRXOG EH LQSXW DIWHU PLQLPXP W5& LV PHW DQG GDWD EXV LV LQ +LJK=
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
133
Preliminary
Synchronous Operation - Clock Input (Burst Mode)
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
5/ &ORFN 3HULRG 5/ 5/ 5/ &ORFN +LJK 7LPH &ORFN /RZ 7LPH &ORFN 5LVH)DOO 7LPH
1RWHV
W&.+ W&./ W&.7 W&.
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Synchronous Operation - Address Latch (Burst Mode)
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
$GGUHVV 6HWXS 7LPH WR $'9 $GGUHVV 6HWXS 7LPH WR &( $GGUHVV +ROG 7LPH IURP $'9 $'9 $'9 /RZ 3XOVH :LGWK /RZ 6HWXS 7LPH WR &/.
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134
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Synchronous Read Operation (Burst Mode)
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
%XUVW 5HDG &\FOH 7LPH &/. $FFHVV 7LPH 2XWSXW +ROG 7LPH IURP &/. &( 2( $'9 /RZ WR :$,7 /RZ WR :$,7 /RZ WR :$,7 /RZ /RZ /RZ 5/ 5/
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
135
Preliminary
Synchronous Write Operation (Burst Mode)
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
%XUVW :ULWH &\FOH 7LPH 'DWD 6HWXS 7LPH WR &ORFN 'DWD +ROG 7LPH IURP &/. :( /RZ 6HWXS 7LPH WR VW 'DWD ,Q 6HWXS 7LPH IRU :ULWH
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136
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Power Down Parameters
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
&( /RZ 6HWXS 7LPH IRU 3RZHU 'RZQ (QWU\ &( /RZ +ROG 7LPH DIWHU 3RZHU 'RZQ (QWU\ &( /RZ +ROG 7LPH IRU 5HVHW WR $V\QFKURQRXV 0RGH &( +LJK +ROG 7LPH IROORZLQJ &( +LJK DIWHU 3RZHU 'RZQ ([LW >6/((3 PRGH RQO\@ &( +LJK +ROG 7LPH IROORZLQJ &( +LJK DIWHU 3RZHU 'RZQ ([LW >QRW LQ 6/((3 PRGH@ &( +LJK 6HWXS 7LPH IROORZLQJ &( +LJK DIWHU 3RZHU 'RZQ ([LW
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Other Timing Parameters
32M Parameter Symbol Min. Max. Min. 64M Max. Unit Notes
&( +LJK WR 2( ,QYDOLG 7LPH IRU 6WDQGE\ (QWU\ &( +LJK WR :( ,QYDOLG 7LPH IRU 6WDQGE\ (QWU\ &( /RZ +ROG 7LPH DIWHU 3RZHUXS &( +LJK +ROG 7LPH IROORZLQJ &( +LJK DIWHU 3RZHUXS ,QSXW 7UDQVLWLRQ 7LPH
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AC Test Conditions
Symbol Description Test Setup Value Unit Note
9,+ 9,/ 95() W7
,QSXW +LJK /HYHO ,QSXW /RZ /HYHO ,QSXW 7LPLQJ 0HDVXUHPHQW /HYHO ,QSXW 7UDQVLWLRQ 7LPH $V\QF 6\QF %HWZHHQ 9,/ DQG 9,+
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
137
Preliminary
AC Measurement Output Load Circuit
VDD*0.5V 50ohm VDD 0.1F VSS DEVICE UNDER TEST 50pF OUT
Figure 49.
Output Load Circuit
138
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Timing Diagrams
tRC ADDRESS ADDRESS VALID
ADV#
Low tASC tCE tCHAH tCP tOE tCHZ tASC
CE1#
OE# tOHZ LB# / UB# tBLZ DQ (Output) tOLZ tBA tBHZ
VALID DATA OUTPUT
tOH
Figure 50. Asynchronous Read Timing #1-1 (Basic Timing)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG :( +
tRC ADDRESS ADDRESS VALID tAV ADV# tASC tCE CE1# tOE OE# tOHZ LB# / UB# tBLZ DQ (Output) tOLZ tBA tBHZ tCP tCHZ tVPL tASC tAHV
VALID DATA OUTPUT
tOH
Figure 51.
Asynchronous Read Timing #1-2 (Basic Timing)
+
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG :(
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
139
Preliminary
tRC ADDRESS ADDRESS VALID tAA CE1# Low tASO OE# tOE
tAX
tRC ADDRESS VALID tAA tOHAH
LB# / UB# tOLZ DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT tOH tOH tOHZ
Figure 52. Asynchronous Read Timing #2 (OE# & Address Access)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 / DQG :( +
tAX ADDRESS tAA CE1#, OE# LB# Low tBA
tRC ADDRESS VALID
tAX
tBA
tBA UB# tBLZ DQ1-8 (Output) DQ9-16 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH
VALID DATA OUTPUT
Figure 53.
Asynchronous Read Timing #3 (LB# / UB# Byte Access)
/ DQG :( +
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9
140
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
tRC ADDRESS (A21-A3) tRC ADDRESS (A2-A0) tASC ADV# CE1# OE# LB# / UB# tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access) VALID DATA OUTPUT (Page Access) tOH tOH tOH tOH tCE ADDRESS VALID ADDRESS VALID tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPAA
tPAA
tPAA
tCHAH
tCHZ
Figure 54. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG :( +
tRC ADDRESS (A21-A3) ADDRESS (A2-A0) CE1# ADDRESS VALID tRC
ADDRESS VALID
tAX
tRC ADDRESS VALID
tAX
tPRC
ADDRESS VALID
tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tAA Low tASO OE# tBA LB# / UB# DQ (Output) tOLZ tBLZ tOH tOE
tPAA
tAA
tPAA
tOH
tOH
tOH
VALID DATA OUTPUT (Normal Access)
VALID DATA OUTPUT (Page Access)
Figure 55.
1RWHV
Asynchronous Read Timing #5 (Random and Page Address Access)
/ DQG :( + DQG 2( DUH /RZ
7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 (LWKHU RU ERWK /% DQG 8%
PXVW EH /RZ ZKHQ ERWK &(
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
141
Preliminary
tWC ADDRESS ADV# Low tAS CE1# tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT tDS tDH tBW tBR tAS tWP tWR tAS tCW tWRC tAS ADDRESS VALID
Figure 56.
Asynchronous Write Timing #1-1 (Basic Timing)
/
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9
tWC ADDRESS ADDRESS VALID tVPL tAS CE1# tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT tDS tDH tBW tBR tAS tWP tWR tAS tAHV tCW tWRC tAS
ADV#
Figure 57. Asynchronous Write Timing #1-2 (Basic Timing)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( +
142
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
tWC ADDRESS tOHAH CE1# Low tAS WE# tWP tWR tAS ADDRESS VALID
tWC ADDRESS VALID
tWP
tWR
UB#, LB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT VALID DATA INPUT tDS tDH tDS tDH
Figure 58. Asynchronous Write Timing #2 (WE# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9 /
tWC ADDRESS CE1# Low tAS WE# tBR LB# tBS UB# tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input) tDH tBH tWP tAS ADDRESS VALID
tWC ADDRESS VALID
tWP tBH
tBS
tBR
tDS
tDH
VALID DATA INPUT
Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 / DQG 2( +
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
143
Preliminary
tWC ADDRESS CE1# Low tWR WE# tAS LB# tBS UB# tDS DQ1-8 (Input) DQ9-16 (Input) tDH tBH tAS tBW tBS ADDRESS VALID
tWC ADDRESS VALID
tWR
tBH
tBW
VALID DATA INPUT
tDS
tDH
VALID DATA INPUT
Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 / DQG 2( +
tWC ADDRESS CE1# Low ADDRESS VALID
tWC ADDRESS VALID
WE# tAS LB# tBS UB# tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBR tBW tBR tBS tBH
Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 / DQG 2( +
144
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
tWC ADDRESS CE1# Low ADDRESS VALID
tWC ADDRESS VALID
WE# tAS LB# tBWO DQ1-8 (Input) tAS UB# tDS DQ9-16 (Input) tDH tDS tDH tDS tDH tBW tBR tAS tBW tBR
VALID DATA INPUT
VALID DATA INPUT
tBW
tBR
tAS
tBWO tBW tDS
tBR
tDH
VALID DATA INPUT
VALID DATA INPUT
Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + $'9 / DQG 2( +
tWC ADDRESS tCHAH CE1# tCP WE# tCP tAS WRITE ADDRESS tCW tWRC tASC
tRC READ ADDRESS tCE tCHAH
UB#, LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tCLZ tOH
Figure 63.
1RWHV
Asynchronous Read / Write Timing #1-1 (CE1# Control)
/ RI ODVW IDOOLQJ HGJH
7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9 :ULWH DGGUHVV LV YDOLG IURP HLWKHU &( RU :(
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
145
Preliminary
tWC ADDRESS tCHAH CE1# tCP tWP WE# tCP tAS WRITE ADDRESS tWR tASC
tRC READ ADDRESS tCE tCHAH
UB#, LB# tOHCL OE tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tOLZ tOH tOE
Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)
1RWHV
2( 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9 / FRQWUROOHG ZULWH DW 5HDG:ULWH5HDG 6HTXHQFH
FDQ EH IL[HG /RZ GXULQJ ZULWH RSHUDWLRQ LI LW LV &(
tWC ADDRESS tOHAH CE1# Low tAS WE# tOES tWP tWR WRITE ADDRESS
tRC READ ADDRESS tAA tOHAH
UB#, LB# tASO OE# tOHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tOLZ tOHZ tOH tOE
Figure 65.
1RWHV
&(
Asynchronous Read / Write Timing #2 (OE#, WE# Control)
/
7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9 FDQ EH WLHG WR /RZ IRU :( DQG 2(
FRQWUROOHG RSHUDWLRQ
146
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
tWC ADDRESS WRITE ADDRESS
tRC READ ADDRESS tAA
CE1#
Low
tOHAH
tOHAH
WE# tOES UB#, LB# tBHZ OE# tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tBLZ tBHZ tOH tASO tAS tBW tBR tBA
Figure 66.
1RWHV
&(
Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)
/
7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG $'9 FDQ EH WLHG WR /RZ IRU :( DQG 2(
FRQWUROOHG RSHUDWLRQ
tCK CLK
tCK
tCKH
tCKL
tCKT
tCKT
Figure 67. Clock Input Timing
1RWHV
6WDEOH FORFN LQSXW PXVW EH UHTXLUHG GXULQJ &( W&. LV GHILQHG EHWZHHQ YDOLG FORFN HGJHV W&.7 LV GHILQHG EHWZHHQ 9,+ 0LQ DQG 9,/ 0D[ /
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
147
Preliminary
Case #1
CLK
Case #2
ADDRESS tASCL tVSCK ADV# tVLCL tCLCK CE1#
Valid tCKVH tAHV tASVL tVSCK
Valid tCKVH tAHV
tVPL
tVPL
Low
Figure 68. Address Latch Timing (Synchronous Mode)
1RWHV
&DVH LV WKH WLPLQJ ZKHQ &( LV EURXJKW WR /RZ DIWHU $'9 EURXJKW WR /RZ DIWHU &( LV EURXJKW WR /RZ W93/ LV VSHFLILHG IURP WKH QHJDWLYH HGJH RI HLWKHU &( LQSXW GXULQJ $'9 / RU $'9 LV EURXJKW WR /RZ &DVH LV WKH WLPLQJ ZKHQ $'9 LV
ZKLFKHYHU FRPHV ODWH $W OHDVW RQH YDOLG FORFN HGJH PXVW EH /
W96&. DQG W&/&. DUH DSSOLHG WR WKH VW YDOLG FORFN HGJH GXULQJ $'9
148
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCLCK tCKOH tCP OE# tOLQ WE# High tCKBH LB#, UB# tBLQ tCKTV tOHTZ tCLCK tVHVL tVPL tASCL Valid tAHV tASVL tVSCK tCKVH Valid
tCKTV
WAIT#
High-Z tOLTL tCKTX tAC tAC Q1 tOLZ tCKQX tAC tCKTX QBL tCKQX tOHZ
DQ
High-Z
Figure 69.
32M Synchronous Read Timing #1 (OE# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
149
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCP tCLCK tCKCLH OE# tCLCK tVHVL tVPL tASCL Valid tAHV tASVL tVSCK tCKVH Valid tAHV
WE#
High tCKBH
LB#, UB# tCKTV tCKTV tCHTZ WAIT# tCLTL DQ tCLZ tCKTX tAC tAC Q1 tCKQX tAC tCKTX QBL tCKQX tCHZ tCLZ tCLTL
Figure 70.
32M Synchronous Read Timing #2 (CE1# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
150
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tVHVL tVPL CE1# Low Valid tAHV tASVL tVSCK tCKVH Valid tAHV
OE#
Low
WE#
High
LB#, UB# tCKTV tCKTV
WAIT# tCKTX DQ tAC tAC Q1 tCKQX tAC tCKTX QBL tCKQX
Figure 71. 32M Synchronous Read Timing #3 (ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
151
Preliminary
RL=5
CLK
ADDRESS
XXX7Fh tAHV tVSCK tCKVH
tASVL
ADV#
tVPL tASCL
CE1#
tCLCK
OE#
tOLQ
WE#
High
tBLQ
LB#, UB#
tCKTV
tCKTV
tCKTV
WAIT#
High-Z tCKTX tOLTL tCKTX tAC tAC Q1 tOLZ tCKQX tCKTX tAC tAC Q2 tCKQX tAC Q3 tCKQX
DQ
High-Z
Figure 72. Synchronous Read - WAIT# Output Timing (Continuous Read)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
152
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCLCK tCKOH tCP OE# tOLQ WE# High tCKBH tBLQ LB#, UB# tCKTV tOHTZ tCLCK tVHVL tVPL tASCL Valid tAHV tASVL tVSCK tCKVH Valid
WAIT#
High-Z tOLTL tCKTX tAC tAC Q1 tOLZ tCKQX tAC QBL tCKQX tOHZ
DQ
High-Z
Figure 73.
64M Synchronous Read Timing #1 (OE# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
153
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK ADV# tVPL tASCL CE1# tCP tCLCK tCKCLH OE# tCLCK tVHVL tVPL tASCL Valid tAHV tCKVH tASVL tVSCK tCKVH Valid tAHV
WE#
High tCKBH
LB#, UB# tCKTV tCHTZ WAIT# tCLTL DQ tCLZ tCKTX tAC tAC Q1 tCKQX tAC QBL tCKQX tCHZ tCLZ tCLTL
Figure 74.
64M Synchronous Read Timing #2 (CE1# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
154
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tRCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tVHVL tVPL CE1# Low Valid tAHV tASVL tVSCK tCKVH Valid tAHV
OE#
Low
WE#
High
LB#, UB# tCKTV tVLTL WAIT# tCKTX DQ tAC tAC Q1 tCKQX tAC QBL tCKQX tVLTL
Figure 75. 64M Synchronous Read Timing #3 (ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
155
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCLCK tCP tVHVL tWRB tASCL tVPL tCLCK Valid tAHV tASVL tVSCK tCKVH Valid tAHV
OE#
High tWLD tCKWH
WE# tBS LB#, UB# tCKBH tBS
WAIT#
High-Z tWLTH tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tWHTZ
DQ
Figure 76. Synchronous Write Timing #1 (WE# Level Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
156
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCLCK tCP tCKCLH tVHVL tWRB tASCL tVPL tCLCK Valid tAHV tASVL tVSCK tCKVH Valid tAHV
OE#
High tWSCK tCKWH tWSCK tCKWH
WE# tBS LB#, UB# tCKBH tBS
WAIT#
High-Z tWLTH tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tCHTZ tWLTH
DQ
Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
157
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tVHVL Valid tAHV tASVL tVSCK tCKVH tVPL Valid tAHV
CE1#
tWRB
OE#
High
WE# tBS LB#, UB# tCKBH tBS
High WAIT# tDSCK DQ D1 tDHCK tDSCK D2 tDSCK DBL tDHCK
Figure 78. Synchronous Write Timing #3 (ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
158
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVPL tASCL CE1# tCLCK tCP tVHVL tWRB tASCL tVPL tCLCK Valid tAHV tASVL tVSCK tCKVH Valid tAHV
OE#
High tWLD tCKWH
WE# tBS LB#, UB# tCKBH tBS
WAIT#
High-Z tWLTH tDSCK D1 tDHCK tWHTZ tWLTH
DQ
Figure 79. Synchronous Write Timing #4 (WE# Level Control, Single Write)
1RWHV
7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG VLQJOH ZULWH RSHUDWLRQ :ULWH GDWD LV ODWFKHG RQ WKH YDOLG FORFN HGJH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
159
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVHVL tCKCLH CE1# tCP OE# tASCL tVPL tCLCK tCKCLH Valid tAHV
WE# tCKBH LB#, UB# tCKTV WAIT# tAC DQ QBL-1 tCKQX tCKTX QBL tCKQX tCHZ tCLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tCHTZ tBS tCKBH
Figure 80.
32M Synchronous Read to Write Timing #1(CE1# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
160
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK
ADDRESS tASVL
Valid tAHV tVSCK tCKVH
ADV# tVPL tVHVL CE1#
tCKOH OE# tWLD tCKWH
WE# tCKBH LB#, UB# tOHTZ tCKTV WAIT# tOHZ tAC DQ QBL-1 tCKQX tCKTX QBL tCKQX tWLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH
Figure 81. 32M Synchronous Read to Write Timing #2(ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
161
Preliminary
RL=5 CLK tWCB ADDRESS tASVL tVSCK tCKVH ADV# tVHVL tCKCLH CE1# tCP OE# tASCL tVPL tCLCK tCKCLH Valid tAHV
WE# tCKBH LB#, UB# tCHTZ WAIT# tCHZ tAC DQ QBL-1 tCKQX QBL tCKQX tCLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH
Figure 82. 64M Synchronous Read to Write Timing #1(CE1# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
162
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK
ADDRESS tASVL
Valid tAHV tVSCK tCKVH
ADV# tVPL tVHVL CE1#
tCKOH OE# tWLD tCKWH
WE# tCKBH LB#, UB# tOHTZ WAIT# tOHZ tAC DQ QBL-1 tCKQX QBL tCKQX tWLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH
Figure 83. 64M Synchronous Read to Write Timing #2(ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
163
Preliminary
RL=5 CLK tCKT ADDRESS tASVL tVSCK tCKVH ADV# tVPL tCKCLH CE1# tCP tWRB OE# tCLCK tASCL
Valid tAHV
WE# tCKBH LB#, UB# tCKTV
WAIT# tDSCK DQ DBL-1 tDHCK tDSCK DBL tDHCK tCHTZ
High-Z tCLTL tCKTX tAC tAC Q1 tCLZ tCKQX Q2 tCKQX
Figure 84. Synchronous Write to Read Timing #1 (CE1# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
164
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
RL=5 CLK tCKT ADDRESS tASVL tVSCK tCKVH ADV# tVPL tWRB CE1# Low
Valid tAHV
OE# tOLQ tCKWH WE# tCKBH tBLQ LB#, UB# tCKTV
WAIT# tDSCK DQ DBL-1 tDHCK tDSCK DBL tDHCK tWHTZ
High-Z tOLTL tCKTX tAC tAC Q1 tOLZ tCKQX Q2 tCKQX
Figure 85. Synchronous Write to Read Timing #2 (ADV# Control)
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + WKH YDOLG FORFN HGJH RQ ULVLQJ HGJH DQG %/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
165
Preliminary
CE1# tCHS tC2LH CE2 tCHH
VDD
0V
VDD min
Figure 86. Power-up Timing #1
1RWH 7KH W&/+ VSHFLILHV DIWHU 9'' UHDFKHV VSHFLILHG PLQLPXP OHYHO
CE1# tCHH CE2
VDD
0V
VDD min
Figure 87.
Power-up Timing #2
DQG &(
1RWH 7KH W&++ VSHFLILHV DIWHU 9'' UHDFKHV VSHFLILHG PLQLPXP OHYHO DQG DSSOLFDEOH WR ERWK &(
CE1# tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Figure 88. Power Down Entry and Exit Timing
1RWH 7KLV 3RZHU 'RZQ PRGH FDQ EH DOVR XVHG DV D UHVHW WLPLQJ LI WKH 32:(583 WLPLQJ DERYH FRXOG QRW EH VDWLVILHG DQG 3RZHU'RZQ SURJUDP ZDV QRW SHUIRUPHG SULRU WR WKLV UHVHW
166
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
CE1# tCHOX OE# tCHWX
WE# Active (Read) Standby Active (Write) Standby
Figure 89.
Standby Entry Timing after Read or Write
1RWH %RWK W&+2; DQG W&+:; GHILQH WKH HDUOLHVW HQWU\ WLPLQJ IRU 6WDQGE\ PRGH ,I HLWKHU RI WLPLQJ LV QRW VDWLVILHG LW WDNHV W5& PLQ SHULRG IRU 6WDQGE\ PRGH IURP &( /RZ WR +LJK WUDQVLWLRQ
tRC ADDRESS MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
tRC Key*2 tCP*3 (tRC)
tCP CE1#
tCP
tCP
tCP
tCP
OE#
WE#
LB#, UB#
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
X Cycle #4
X Cycle #5
RDb Cycle #6
Figure 90.
1RWHV
Configuration Register Set Timing #1 (Asynchronous Operation)
WR
7KH DOO DGGUHVV LQSXWV PXVW EH +LJK IURP &\FOH
7KH DGGUHVV NH\ PXVW FRQILUP WKH IRUPDW VSHFLILHG LQ WKH )XQFWLRQDO 'HVFULSWLRQ VHFWLRQ ,I QRW WKH RSHUDWLRQ DQG GDWD DUH QRW JXDUDQWHHG $IWHU W&3 RU W5& IROORZLQJ &\FOH WKH &RQILJXUDWLRQ 5HJLVWHU 6HW LV FRPSOHWHG DQG UHWXUQHG WR WKH QRUPDO RSHUDWLRQ W&3 DQG W5& DUH DSSOLFDEOH WR UHWXUQLQJ WR DV\QFKURQRXV PRGH DQG WR V\QFKURQRXV PRGH UHVSHFWLYHO\ %\WH UHDG RU ZULWH LV DYDLODEOH LQ DGGLWLRQ WR :RUG UHDG RU ZULWH $W OHDVW RQH E\WH FRQWURO VLJQDO /% /RZ RU 8% QHHG WR EH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
167
Preliminary
CLK
ADDRESS MSB tRCB ADV# tTRB
MSB tWCB
MSB tWCB
MSB tWCB
MSB tWCB
Key tRCB
tTRB
tTRB
tTRB
tTRB
tTRB
CE1#
OE#
WE#
LB#, UB#
WAIT# RL DQ RDa Cycle#1 RL-1 RDa Cycle#2 RL-1 RDa Cycle#3 RL-1 X Cycle#4 RL-1 X Cycle#5 RL RDb Cycle#6
Figure 91. Configuration Register Set Timing #2 (Synchronous Operation)
1RWHV
7KH DOO DGGUHVV LQSXWV PXVW EH +LJK IURP &\FOH WR
7KH DGGUHVV NH\ PXVW FRQILUP WKH IRUPDW VSHFLILHG LQ WKH )XQFWLRQDO 'HVFULSWLRQ VHFWLRQ ,I QRW WKH RSHUDWLRQ DQG GDWD DUH QRW JXDUDQWHHG $IWHU W75% IROORZLQJ &\FOH WKH &RQILJXUDWLRQ 5HJLVWHU 6HW LV FRPSOHWHG DQG UHWXUQHG WR WKH QRUPDO RSHUDWLRQ RU 8% QHHG WR EH %\WH UHDG RU ZULWH LV DYDLODEOH LQ DGGLWLRQ WR :RUG UHDG RU ZULWH $W OHDVW RQH E\WH FRQWURO VLJQDO /% /RZ
168
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
COSMORAM Type 1 - 1.8 V, 16 Mb
CMOS 1,048,576-Word x 16 Bit pSRAM
PRELIMINARY
Features
$V\QFKURQRXV 65$0 ,QWHUIDFH )DVW 5DQGRP $FFHVV 7LPH
W&( 9'' 7$ QV 9 WR 9 & WR &
/RZ 9ROWDJH 2SHUDWLQJ &RQGLWLRQ :LGH 2SHUDWLQJ 7HPSHUDWXUH %\WH &RQWURO E\ 8%
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DQG /%
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3RZHU 'RZQ 0RGH
General Description
7KH &26025$0 7\SH LV D &026 S65$0 ZLWK DV\QFKURQRXV 6WDWLF 5DQGRP $FFHVV 0HPRU\ 65$0 LQWHUIDFH FRQWDLQLQJ VWRUDJHV DFFHVVLEOH LQ D ELW IRUPDW 7KLV &26025$0 7\SH LV VXLWHG IRU PRELOH DSSOLFDWLRQV VXFK DV &HOOXODU +DQGVHW DQG 3'$
Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
Preliminary
Pin Description
3LQ 1DPH $ WR $ &( &( :( 2( 8% 'HVFULSWLRQ $GGUHVV ,QSXW &KLS (QDEOH /RZ $FWLYH &KLS (QDEOH +LJK $FWLYH :ULWH (QDEOH /RZ $FWLYH 2XWSXW (QDEOH /RZ $FWLYH 8SSHU %\WH &RQWURO /RZ $FWLYH 3LQ 1DPH /% '4 '4 9'' 966 'HVFULSWLRQ /RZHU %\WH &RQWURO /RZ $FWLYH 8SSHU %\WH 'DWD ,QSXW2XWSXW /RZHU %\WH 'DWD ,QSXW2XWSXW 3RZHU 6XSSO\ *URXQG
Block Diagram
9'' 966 $ $ $GGUHVV /DWFK DQG %XIIHU 5RZ 'HFRGHU 0HPRU\ &HOO $UUD\ %LW
'4 '4
,QSXW 2XWSXW %XIIHU
,QSXW 'DWD /DWFK DQG &RQWURO
6HQVH 6ZLWFK &ROXPQ 'HFRGHU
2XWSXW 'DWD &RQWURO
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$GGUHVV /DWFK %XIIHU
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3RZHU &RQWURO 7LPLQJ &RQWURO
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170
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Function Truth Table
A
0RGH 6WDQGE\ 'HVHOHFW 2XWSXW 'LVDEOH 1RWH 2XWSXW 'LVDEOH 1R 5HDG 5HDG 8SSHU %\WH 5HDG /RZHU %\WH 5HDG :RUG 1R :ULWH :ULWH 8SSHU %\WH :ULWH /RZHU %\WH :ULWH :RUG 3RZHU 'RZQ1RWH
&( +
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8% ; ; + / + / + / + / ;
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'4 +LJK= +LJK= +LJK= +LJK= 2XWSXW 9DOLG 2XWSXW 9DOLG ,QYDOLG ,QYDOLG ,QSXW 9DOLG ,QSXW 9DOLG +LJK=
'4 +LJK= +LJK= +LJK= 2XWSXW 9DOLG +LJK= 2XWSXW 9DOLG ,QYDOLG ,QSXW 9DOLG ,QYDOLG ,QSXW 9DOLG +LJK=
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7KLV ORJLF FRQGLWLRQ VKRXOG QRW EH NHSW DQ\ ORQJHU WKDQ V 3RZHU 'RZQ PRGH FDQ EH HQWHUHG IURP 6WDQGE\ VWDWH DQG DOO '4 SLQV DUH LQ +LJK= VWDWH &DQ EH HLWKHU 9,/ RU 9,+ EXW PXVW EH YDOLG EHIRUH 5HDG RU :ULWH
Absolute Maximum Ratings
3DUDPHWHU 9ROWDJH RI 9'' 6XSSO\ 5HODWLYH WR 966 9ROWDJH DW $Q\ 3LQ 5HODWLYH WR 966 6KRUW &LUFXLW 2XWSXW &XUUHQW 6WRUDJH 7HPSHUDWXUH 6\PERO 9'' 9,1 9287 ,287 767* 9DOXH WR WR + WR 8QLW 9 9 P$ &
1RWH 6HPLFRQGXFWRU GHYLFHV FDQ EH SHUPDQHQWO\ GDPDJHG E\ DSSOLFDWLRQ RI VWUHVV YROWDJH FXUUHQW WHPSHUDWXUH DQG
VR RQ LQ H[FHVV RI DEVROXWH PD[LPXP UDWLQJV 'R QRW H[FHHG WKHVH UDWLQJV
Recommended Operating Conditions
3DUDPHWHU 6XSSO\ 9ROWDJH +LJK /HYHO ,QSXW 9ROWDJH 1RWH /RZ /HYHO ,QSXW 9ROWDJH 1RWH $PELHQW 7HPSHUDWXUH 6\PERO 9'' 966 9,+ 9,/ 7$ 0LQ 9'' 0D[ 9'' 9'' 8QLW 9 9 9 9 &
1RWHV 5HIHUHQFHG WR 966

0D[LPXP '& YROWDJH RQ LQSXW DQG ,2 SLQV DUH 9'' 9 'XULQJ YROWDJH WUDQVLWLRQV LQSXWV PD\ RYHUVKRRW WR 9'' 9 IRU SHULRGV RI XS WR QV 0LQLPXP '& YROWDJH RQ LQSXW RU ,2 SLQV DUH 9 'XULQJ YROWDJH WUDQVLWLRQV LQSXWV PD\ RYHUVKRRW 966 WR 9 IRU SHULRGV RI XS WR QV 5HFRPPHQGHG RSHUDWLQJ FRQGLWLRQV DUH QRUPDO RSHUDWLQJ UDQJHV IRU WKH VHPLFRQGXFWRU GHYLFH $OO WKH GHYLFH HOHFWULFDO FKDUDFWHULVWLFV DUH ZDUUDQWHG ZKHQ RSHUDWHG ZLWKLQ WKHVH UDQJHV $OZD\V XVH VHPLFRQGXFWRU GHYLFHV ZLWKLQ WKH UHFRPPHQGHG RSHUDWLQJ FRQGLWLRQV 2SHUDWLRQ RXWVLGH WKHVH UDQJHV PD\ DIIHFW GHYLFH UHOLDELOLW\ DQG UHVXOW LQ GHYLFH IDLOXUH 1R ZDUUDQW\ LV PDGH ZLWK UHVSHFW WR XVHV RSHUDWLQJ FRQGLWLRQV RU FRPELQDWLRQV QRW UHSUHVHQWHG RQ WKH GDWD VKHHW
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
171
Preliminary
Package Pin Capacitance
6\PERO &,1 &,1 &,2 'HVFULSWLRQ $GGUHVV ,QSXW &DSDFLWDQFH &RQWURO ,QSXW &DSDFLWDQFH 'DWD ,QSXW2XWSXW &DSDFLWDQFH & I 0+] 7HVW 6HWXS 9,1 9,1 9,2 9 9 9 7\S 0D[ 8QLW S) S) S)
1RWH 7HVW FRQGLWLRQV 7$
DC Characteristics
3DUDPHWHU ,QSXW /HDNDJH &XUUHQW 2XWSXW /HDNDJH &XUUHQW 2XWSXW +LJK 9ROWDJH /HYHO 2XWSXW /RZ 9ROWDJH /HYHO 9'' 3RZHU 'RZQ &XUUHQW 9'' 6WDQGE\ &XUUHQW 6\PER O ,/, ,/2 92+ 92/ ,''36 ,''6 ,''6 ,''$ ,''$ 9,1 9287 9'' ,2/ 9'' 9'' 966 WR 9'' 966 WR 9'' 2XWSXW 'LVDEOH 9''PLQ ,2+ P$ 9'' PD[ 9,1 9'' PD[ 9,1 9,+ RU 9,/ &( 9 9,+ RU 9,/ &( &( 9,+ P$ 7HVW &RQGLWLRQV 0LQ 0D[ 8QLW PLQLPXP V $ $ 9 9 $ P$ $ P$ P$
9'' 9'' PD[ 9,1 9 RU 9,1 9'' 9 &( &( ! 9'' 9 W5& W:& 9'' 9'' PD[ 9,1 9,+ RU 9,/ &( 9,/ DQG &( 9,+ ,287 P$ W W 5& :&
9'' $FWLYH &XUUHQW

1RWHV
$OO YROWDJHV DUH UHIHUHQFHG WR 966 '& &KDUDFWHULVWLFV DUH PHDVXUHG DIWHU IROORZLQJ SRZHUXS WLPLQJ ,287 GHSHQGV RQ WKH RXWSXW ORDG FRQGLWLRQV '& &KDUDFWHULVWLFV DSSO\ XQGHU UHFRPPHQGHG RSHUDWLQJ FRQGLWLRQV XQOHVV RWKHUZLVH QRWHG
AC Characteristics
Read Operation
A
3DUDPHWHU 1RWHV 5HDG &\FOH 7LPH &( $FFHVV 7LPH 2( /% $FFHVV 7LPH 8% $FFHVV 7LPH $GGUHVV $FFHVV 7LPH 2XWSXW 'DWD +ROG 7LPH &( /RZ WR 2XWSXW /RZ= 2( /% 2( /% /RZ WR 2XWSXW /RZ= 8% /RZ WR 2XWSXW /RZ=
6\PERO W5& W&( W2( W$$ W%$ W2+ W&/= W2/= W%/= W&+= W2+= W%+= W$6& W$62 W$; W&+$+ W2+$+ +LJK
9DOXH 0LQ 0D[
8QLW QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV
&( +LJK WR 2XWSXW +LJK= +LJK WR 2XWSXW +LJK= 8% +LJK WR 2XWSXW +LJK= /RZ
$GGUHVV 6HWXS 7LPH WR &( /RZ $GGUHVV 6HWXS 7LPH WR 2( $GGUHVV ,QYDOLG 7LPH $GGUHVV +ROG 7LPH IURP &( +LJK $GGUHVV +ROG 7LPH IURP 2(
172
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
3DUDPHWHU 1RWHV :( +LJK WR 2( /RZ 7LPH IRU 5HDG
6\PERO W:+2/ W&3
9DOXH 0LQ 0D[
8QLW QV QV
&( +LJK 3XOVH :LGWK

1RWHV
0D[LPXP YDOXH LV DSSOLFDEOH LI &( LV NHSW DW /RZ ZLWKRXW DQ\ DGGUHVV FKDQJH $GGUHVV VKRXOG QRW EH FKDQJHG ZLWKLQ PLQLPXP W5& 7KH RXWSXW ORDG S) ZLWK WHUPLQDWLRQ WR 9'' 9 7KH RXWSXW ORDG S) ZLWKRXW DQ\ RWKHU ORDG $SSOLFDEOH ZKHQ &( LV NHSW DW /RZ W5& PLQ PXVW EH VDWLVILHG ,I DFWXDO YDOXH RI W:+2/ LV VKRUWHU WKDQ VSHFLILHG PLQLPXP YDOXHV WKH DFWXDO W$$ RI IROORZLQJ 5HDG PD\ EHFRPH ORQJHU E\ WKH DPRXQW RI VXEWUDFWLQJ DFWXDO YDOXH IURP VSHFLILHG PLQLPXP YDOXH $& &KDUDFWHULVWLFV DSSO\ XQGHU UHFRPPHQGHG RSHUDWLQJ FRQGLWLRQV XQOHVV RWKHUZLVH QRWHG
Write Operation
3DUDPHWHU 1RWHV :ULWH &\FOH 7LPH $GGUHVV 6HWXS 7LPH &( :ULWH 3XOVH :LGWK :( /% /% /% :ULWH 3XOVH :LGWK 8% 8% 8% :ULWH 3XOVH :LGWK %\WH 0DVN 6HWXS 7LPH %\WH 0DVN +ROG 7LPH 6\PERO W:& W$6 W&: W:3 W%: W%6 W%+ W:5 W&3 W:+3 W%+3 W'6 W'+ W2+&/ W2(6 W%:2 9DOXH 0LQ 0D[ 8QLW QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV QV
:ULWH 5HFRYHU\ 7LPH &( +LJK 3XOVH :LGWK :( /% +LJK 3XOVH :LGWK 8% +LJK 3XOVH :LGWK
'DWD 6HWXS 7LPH 'DWD +ROG 7LPH 2( 2( /% +LJK WR &( /RZ 6HWXS 7LPH IRU :ULWH +LJK WR $GGUHVV 6HWXS 7LPH IRU :ULWH DQG 8% :ULWH 3XOVH 2YHUODS
1RWHV

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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
173
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Power Down Parameters
3DUDPHWHU 1RWHV &( /RZ 6HWXS 7LPH IRU 3RZHU 'RZQ (QWU\ &( /RZ +ROG 7LPH DIWHU 3RZHU 'RZQ (QWU\ &( +LJK +ROG 7LPH IROORZLQJ &( +LJK DIWHU 3RZHU 'RZQ ([LW >6/((3 PRGH RQO\@ 6HH 1RWH &( +LJK 6HWXS 7LPH IROORZLQJ &( +LJK DIWHU 3RZHU 'RZQ ([LW 6\PERO W&63 W&/3 W&++ W&+6 9DOXH 0LQ 0D[ 8QLW QV QV V QV
1RWH $SSOLFDEOH DOVR WR SRZHUXS
Other Timing Parameters
3DUDPHWHU 1RWHV &( +LJK WR 2( &( +LJK WR :( ,QYDOLG 7LPH IRU 6WDQGE\ (QWU\ ,QYDOLG 7LPH IRU 6WDQGE\ (QWU\ 6\PERO W&+2; W&+:; W&++ W7 9DOXH 0LQ 0D[ 8QLW QV QV V QV
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AC Test Conditions
6\PERO 9,+ 9,/ 95() W7 'HVFULSWLRQ ,QSXW +LJK /HYHO ,QSXW /RZ /HYHO ,QSXW 7LPLQJ 0HDVXUHPHQW /HYHO ,QSXW 7UDQVLWLRQ 7LPH %HWZHHQ 9,/ DQG 9,+ 7HVW 6HWXS 9DOXH 9'' 9'' 9'' 8QLW 9 9 9 QV
AC Measurement Output Load Circuit
VDD* 0.5 V VDD 0.1 F VSS Device Under Test 50 pF
50 Out
174
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
Timing Diagrams
A
W5& $GGUHVV W$6& &( W2( 2( W2+= /% 8% W%/= '4 2XWSXW W2/= 9DOLG 'DWD 2XWSXW W&/= W2+ + W%$ W%+= W&(
$GGUHVV 9DOLG W&+$+ W&3 W&+= W$6&
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG :(
Figure 92. Read Timing #1 (Basic Timing)
W5& $GGUHVV $GGUHVV 9DOLG W$$ &( /RZ W$62 2( W2( W$[ W5& $GGUHVV 9DOLG W$$ W2+$+
/% 8% '4 2XWSXW
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W2+ 9DOLG 'DWD 2XWSXW 9DOLG 'DWD 2XWSXW +
W2+
W2+=
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Figure 93. Read Timing #2 (OE# and Address Access)
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
175
Preliminary
W$; $GGUHVV W$$ &( 2( /RZ W%$ /%
W5& $GGUHVV 9DOLG
W$[
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'4 '4 2XWSXW
1RWH 7KLV WLPLQJ GLDJUDP DVVXPHV &( + DQG :(
+
Figure 94. Read Timing #3 (LB# / UB# Byte Access)
W:& $GGUHVV W$6 &( W$6 :( W$6 /% 8% W%: W:5 W%+3 W:3 W:5 W:+3 W$6 $GGUHVV 9DOLG W&: W:5 W&3 W$6 W$6
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Figure 95. Write Timing #1 (Basic Timing)
176
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
Preliminary
W:& $GGUHVV W2+$+ &( /RZ W$6 :( W:3 W:5 W$6
W:& $GGUHVV 9DOLG
$GGUHVV 9DOLG
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Figure 96.
W:& $GGUHVV &(
Write Timing #2 (WE# Control)
W:& $GGUHVV 9DOLG
$GGUHVV 9DOLG
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:(
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Figure 97.
Write Timing #3 - 1 (WE# / LB# / UB# Byte Write Control)
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
177
Preliminary
W:& $GGUHVV &( $GGUHVV 9DOLG
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Figure 98. Write Timing #3 - 2 (WE# / LB# / UB# Byte Write Control)
W:& $GGUHVV &( $GGUHVV 9DOLG W:& $GGUHVV 9DOLG
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:( W$6 /% W%6 8% W'6 '4 '4 ,QSXW '4 '4 ,QSXW W'+ W%: W:5
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Figure 99.
Write Timing #3 - 3 (WE# / LB# / UB# Byte Write Control)
178
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S71WS-J_04_A2 August 19, 2005
Preliminary
W:& $GGUHVV &( $GGUHVV 9DOLG
W:& $GGUHVV 9DOLG
/RZ
:( W$6 /% W%:2 '4 '4 ,QSXW W$6 8% W'6 '4 '4 ,QSXW 9DOLG 'DWD ,QSXW + W'+ W'6 9DOLG 'DWD ,QSXW W%: W:5 W%+3 W$6 W%:2 W%: W'6 9DOLG 'DWD ,QSXW W'+ W'+ W%: W:5 W%+3 W'6 9DOLG 'DWD ,QSXW W:5 W'+ W$6 W%: W:5
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Figure 100.
Write Timing #3 - 4 (WE# / LB# / UB# Byte Write Control)
W:& W5& 5HDG $GGUHVV W:5 W$6& W&( W&+$+
$GGUHVV W&+$+ &( W&3 :( W$6
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Figure 101.
Read / Write Timing #1 - 1 (CE#1 Control)
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
179
Preliminary
W:& $GGUHVV W&+$+ &( W&3 :( W:3 W&3 W$6 :ULWH $GGUHVV W:5 W$6&
W5& 5HDG $GGUHVV W&( W&+$+
8% /% W2+&/ 2( W&+= W2+ '4 5HDG 'DWD 2XWSXW W'6 W'+ W2/= W2+ 5HDG 'DWD 2XWSXW W2(
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Figure 102.
Read / Write Timing #1 - 2 (CE#1 / WE# / OE# Control)
W:& W5& 5HDG $GGUHVV W$$ W2+$+
$GGUHVV W2+$+ &( /RZ W$6 :( W2(6
:ULWH $GGUHVV
W:3
W:5
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W2+= W2+
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Figure 103. Read / Write Timing #2 (OE#, WE# Control)
180
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S71WS-J_04_A2 August 19, 2005
Preliminary
W:& $GGUHVV :ULWH $GGUHVV
W5& 5HDG $GGUHVV W$$
&(
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W%/= 5HDG 'DWD 2XWSXW
W%+= W2+
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Figure 104. Read / Write Timing #3 (OE, WE, LB, UB Control
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Figure 105. Power-Up Timing
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Figure 107.
Standby Entry Timing after Read or Write
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S71WS-J_04_A2 August 19, 2005
Preliminary
COSMORAM Type 1 Revision Summary
Revision A0 (August 2, 2005)
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
183
Preliminary
Revision Summary
Revision A0 (October 27, 2004)
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Revision A1 (July 5, 2005)
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Revision A2 (August 19, 2005)
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
184
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005

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